-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    test_fifos.vhd                                           #
-- #                                                                          #
-- # Component  :    test_fifos : Test Bench for various FIFOs                #
-- #                                                                          #
-- # Model      :    rtl                                                      #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity test_fifos IS
END test_fifos;

ARCHITECTURE rtl OF test_fifos IS

COMPONENT ff_N_W is
        generic(W: INTEGER := 1; --width of FIFO
                N: INTEGER := 8; --length of FIFO
	        K: INTEGER := 2); --threshold for AEF
	port(
		D: in unsigned(W-1 downto 0);
		Q: out unsigned(W-1 downto 0);
		RES, CLK, RDEN, WREN: in std_ulogic;
		F: buffer std_ulogic :='0';
		E: buffer std_ulogic :='1';
		HF, AEF: out std_ulogic
	);
end COMPONENT;

COMPONENT dff_N_W is
        generic(W: INTEGER := 1; --width of FIFO
                N: INTEGER := 8; --length of FIFO
	        K: INTEGER := 2); --threshold for AEF
	port(
		D: in unsigned(W-1 downto 0);
		Q: out unsigned(W-1 downto 0);
		RES, RDCLK, WRCLK, RDEN, WREN: in std_ulogic;
		F: buffer std_ulogic :='0';
		E: buffer std_ulogic :='1';
		HF, AEF: out std_ulogic
	);
end COMPONENT;

 FOR ALL : ff_N_W USE ENTITY WORK.ff_N_W(rtl);
 FOR ALL : dff_N_W USE ENTITY WORK.dff_N_W(rtl);
 
 CONSTANT N : integer := 16;
 CONSTANT W : integer := 8;
 CONSTANT K : integer := 12;
 SIGNAL DIN1,DIN2,DOUT1,DOUT2 : unsigned(W-1 downto 0);
 SIGNAL RESET,CLK,RDEN,WREN,F1,E1,HF1,AEF1,F2,E2,HF2,AEF2 : std_ulogic := '0';
 
 BEGIN

Single_Fifo : ff_N_W
        GENERIC MAP (
                     W=>W,
                     N=>N,
                     K=>K
                    )
	PORT MAP (
		  D=>DIN1,
		  Q=>DOUT1,
		  RES=>RESET,
		  CLK=>CLK,
		  RDEN=>RDEN,
		  WREN=>WREN,
		  F=>F1,
		  E=>E1,
		  HF=>HF1,
		  AEF=>AEF1
		 );

Dual_Fifo : dff_N_W
        GENERIC MAP (
                     W=>W,
                     N=>N,
                     K=>K
                    )
	PORT MAP (
		  D=>DIN2,
		  Q=>DOUT2,
		  RES=>RESET,
		  RDCLK=>CLK,
		  WRCLK=>CLK,
		  RDEN=>RDEN,
		  WREN=>WREN,
		  F=>F2,
		  E=>E2,
		  HF=>HF2,
		  AEF=>AEF2
		 );

CLK <= not CLK AFTER 50 ns;
RESET <= '0', '1' AFTER 120 ns;

RDEN <= '0', '1' AFTER 1500 ns;
WREN <= '1', '0' AFTER 1500 ns;

PROCESS(RESET,CLK)
BEGIN
IF (RESET='0') THEN
	DIN1 <= (OTHERS=>'0');
	DIN2 <= (OTHERS=>'1');
ELSIF (rising_edge(CLK)) THEN
	DIN1 <= DIN1 + "1";
	DIN2 <= DIN2 - "1";
END IF;
END PROCESS;

END rtl;