-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : test_counters.vhd # -- # # -- # Component : test_counters : Test Bench for various counters. # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity test_counters IS END test_counters; ARCHITECTURE rtl OF test_counters IS COMPONENT bdNsr is generic(N: INTEGER := 4); port( DOUT: out unsigned(N-1 downto 0); CLK,DOWN,R: in std_ulogic; COUT: out std_ulogic ); end COMPONENT; COMPONENT buNar is generic(N: INTEGER := 4); port( DOUT: out unsigned(N-1 downto 0); CLK,R,UP: in std_ulogic; COUT: out std_ulogic ); end COMPONENT; COMPONENT budNlr is generic(N: INTEGER := 8); port( DIN: in unsigned(N-1 downto 0); DOUT: out unsigned(N-1 downto 0); CLK,DOWN,LOAD,R,UP: in std_ulogic; COUT: out std_ulogic ); END COMPONENT; COMPONENT gdNsr is generic(N: INTEGER := 4); port( DOUT: out unsigned(N-1 downto 0); CLK,DOWN,R: in std_ulogic; COUT: out std_ulogic ); END COMPONENT; COMPONENT guNar is generic(N: INTEGER := 4); port( DOUT: out unsigned(N-1 downto 0); CLK,R,UP: in std_ulogic; COUT: out std_ulogic ); END COMPONENT; COMPONENT gudNlr is generic(N: INTEGER := 8); port( DIN: in unsigned(N-1 downto 0); DOUT: out unsigned(N-1 downto 0); CLK,DOWN,LOAD,R,UP: in std_ulogic; COUT: out std_ulogic ); END COMPONENT; FOR ALL : bdNsr USE ENTITY WORK.bdNsr(rtl); FOR ALL : buNar USE ENTITY WORK.buNar(rtl); FOR ALL : budNlr USE ENTITY WORK.budNlr(rtl); FOR ALL : gdNsr USE ENTITY WORK.gdNsr(rtl); FOR ALL : guNar USE ENTITY WORK.guNar(rtl); FOR ALL : gudNlr USE ENTITY WORK.gudNlr(rtl); CONSTANT N : integer := 8; SIGNAL DIN3,DIN6,DOUT1,DOUT2,DOUT3,DOUT4,DOUT5,DOUT6 : unsigned(N-1 downto 0); SIGNAL RESET,CLK,LOAD,UP,DOWN : std_ulogic := '0'; SIGNAL COUT1,COUT2,COUT3,COUT4,COUT5,COUT6 : std_ulogic; BEGIN Binary_down_counter : bdNsr GENERIC MAP ( N=>N ) PORT MAP ( DOUT=>DOUT1, CLK=>CLK, DOWN=>DOWN, R=>RESET, COUT=>COUT1 ); Binary_up_counter : buNar GENERIC MAP ( N=>N ) PORT MAP ( DOUT=>DOUT2, CLK=>CLK, UP=>UP, R=>RESET, COUT=>COUT2 ); Binary_up_down_counter : budNlr GENERIC MAP ( N=>N ) PORT MAP ( DIN=>DIN3, DOUT=>DOUT3, CLK=>CLK, DOWN=>DOWN, UP=>UP, LOAD=>LOAD, R=>RESET, COUT=>COUT3 ); Gray_down_counter : gdNsr GENERIC MAP ( N=>N ) PORT MAP ( DOUT=>DOUT4, CLK=>CLK, DOWN=>DOWN, R=>RESET, COUT=>COUT4 ); Gray_up_counter : guNar GENERIC MAP ( N=>N ) PORT MAP ( DOUT=>DOUT5, CLK=>CLK, UP=>UP, R=>RESET, COUT=>COUT5 ); Gray_up_down_counter : gudNlr GENERIC MAP ( N=>N ) PORT MAP ( DIN=>DIN6, DOUT=>DOUT6, CLK=>CLK, DOWN=>DOWN, UP=>UP, LOAD=>LOAD, R=>RESET, COUT=>COUT6 ); DIN3 <= "00000100"; DIN6 <= "00001100"; CLK <= not CLK AFTER 50 ns; RESET <= '1', '0' AFTER 120 ns; LOAD <= '0', '1' AFTER 1000 ns, '0' AFTER 1100 ns; UP <= '0', '1' AFTER 2000 ns; DOWN <= '1', '0' AFTER 2000 ns; END rtl;