-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    counters.vhd                                             #
-- #                                                                          #
-- # Component  :    budNlr : N-bit binary up/down counter                    #
-- #                          with synchronous load and asynchronous reset    #
-- #                                                                          #
-- # Model      :    rtl                                                      #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.ALL;

-- budNlr Entity Description
entity budNlr is
   generic(N: INTEGER := 8);
   port(
      DIN: in unsigned(N-1 downto 0);
      DOUT: out unsigned(N-1 downto 0);
      CLK,DOWN,LOAD,R,UP: in std_ulogic;
      COUT: out std_ulogic
   );
end budNlr;

-- budNlr Architecture Description
architecture rtl of budNlr is
   signal istate : unsigned(N-1 downto 0);
   signal count : unsigned(N downto 0);
 
begin
   count <= ('0' & istate) + "01" when ((UP = '1') and (DOWN = '0')) else
            ('0' & istate) - "01" when ((DOWN = '1') and (UP = '0')) else
            ('0' & istate);
 
   Count_Process: process(CLK,R)
   begin
      if (R = '1') then
         -- reset event
         istate <= (OTHERS => '0');
      elsif (CLK'event and (CLK = '1') and (CLK'last_value = '0')) then
         if (LOAD = '1') then
            -- clocked load event
            istate <= DIN;
         elsif (UP = '1') or (DOWN = '1') then
            -- clocked count up/down event
            istate <= count(N-1 downto 0);
         end if;
      end if;
   end process Count_Process;
    
   -- Assign output values
   DOUT <= istate;
   COUT <= '0' when (DOWN = '0' and UP = '0')
      else '1' when (DOWN = '1' and UP = '1')
      else not count(N) when (DOWN = '1' and UP = '0')
      else count(N);
end rtl;