-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    test_alus.vhd                                            #
-- #                                                                          #
-- # Component  :    test_alus : Test Bench for various arithmetic components.#
-- #                                                                          #
-- # Model      :    rtl                                                      #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity test_alus IS
END test_alus;

ARCHITECTURE rtl OF test_alus IS

COMPONENT addN
   generic(N: INTEGER := 4);
   port(
      A: in std_ulogic_vector(N-1 downto 0);
      B: in std_ulogic_vector(N-1 downto 0);
      D: out std_ulogic_vector(N-1 downto 0);
      CIN: in std_ulogic;
      COUT: out std_ulogic
   );
end COMPONENT;

COMPONENT subN is
   generic(N: INTEGER := 4);
   port(
      A: in std_ulogic_vector(N-1 downto 0);
      B: in std_ulogic_vector(N-1 downto 0);
      D: out std_ulogic_vector(N-1 downto 0);
      CIN: in std_ulogic;
      COUT: out std_ulogic
   );
end COMPONENT;

COMPONENT adsbN is
   generic(N: INTEGER := 4);
   port(
      A: in std_ulogic_vector(N-1 downto 0);
      B: in std_ulogic_vector(N-1 downto 0);
      D: out std_ulogic_vector(N-1 downto 0);
      CIN,SUB: in std_ulogic;
      COUT: out std_ulogic
   );
END COMPONENT;

COMPONENT aluNf is
   generic(N: INTEGER := 4);
   port(
      A: in std_ulogic_vector(N-1 downto 0);
      B: in std_ulogic_vector(N-1 downto 0);
      OP: in std_ulogic_vector(6 downto 0);
      D: out std_ulogic_vector(N-1 downto 0);
      CIN: in std_ulogic;
      COUT,EQ,GT,LT,OV: out std_ulogic
   );
END COMPONENT;

 FOR ALL : addN USE ENTITY WORK.addN(rtl);
 FOR ALL : subN USE ENTITY WORK.subN(rtl);
 FOR ALL : adsbN USE ENTITY WORK.adsbN(rtl);
 FOR ALL : aluNf USE ENTITY WORK.aluNf(rtl);
 
 CONSTANT N : integer := 8;
 SIGNAL A,B,D1,D2,D3,D4 : std_ulogic_vector(N-1 downto 0);
 SIGNAL OP : std_ulogic_vector(6 downto 0);
 SIGNAL CIN,EQ,GT,LT,OV,SUB : std_ulogic;
 
 BEGIN

Adder : addN 
             GENERIC MAP (
                          N=>N
                         )
	     PORT MAP (
		       A=>A,
		       B=>B,
		       CIN=>CIN,
		       D=>D1,
		       COUT=>OPEN
		      );	 

Subtractor : subN 
             GENERIC MAP (
                          N=>N
                         )
	     PORT MAP (
		       A=>A,
		       B=>B,
		       CIN=>CIN,
		       D=>D2,
		       COUT=>OPEN
		      );			   
 
Adder_Subtractor : adsbN 
             GENERIC MAP (
                          N=>N
                         )
	     PORT MAP (
		       A=>A,
		       B=>B,
		       CIN=>CIN,
		       D=>D3,
		       SUB=>SUB,
		       COUT=>OPEN
		      );		
		      
ALU : aluNf
             GENERIC MAP (
                          N=>N
                         )
	     PORT MAP (
		       A=>A,
		       B=>B,
		       CIN=>CIN,
		       OP=>OP,
		       D=>D4,
		       COUT=>OPEN,
		       EQ=>EQ,
		       GT=>GT,
		       LT=>LT,
		       OV=>OV
		      );		      
		      
		      
SUB <= 	'0','1' AFTER 200 ns;
CIN <= '0';

A <= "10101000",
     "01011001" AFTER 100 ns, 
     "11011011" AFTER 200 ns, 
     "01101001" AFTER 300 ns;
B <= "00111000",
     "01001011" AFTER 100 ns, 
     "01010001" AFTER 200 ns, 
     "11001001" AFTER 300 ns;
OP <= "1010101",
      "0011111" AFTER 100 ns,	
      "0101111" AFTER 200 ns,	
      "1000001" AFTER 300 ns;

END rtl;