-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : alus.vhd # -- # # -- # Component : addN : N-Bit Adder # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; -- addN Entity Description entity addN is generic(N: INTEGER := 4); port( A: in std_ulogic_vector(N-1 downto 0); B: in std_ulogic_vector(N-1 downto 0); D: out std_ulogic_vector(N-1 downto 0); CIN: in std_ulogic; COUT: out std_ulogic ); end addN; -- addN Architecture Description architecture rtl of addN is signal pre_D : std_ulogic_vector(N downto 0); signal pre_OV : std_ulogic; begin ARITHMETIC_Process: process(A,B,CIN) variable fct_out : std_ulogic_vector(N downto 0); variable a_ext,b_ext : std_ulogic_vector(N downto 0); variable carry_ext : std_ulogic_vector(1 downto 0); variable msb : integer; begin -- zero extend inputs to include carry bit a_ext := '0' & A; b_ext := '0' & B; carry_ext := '0' & CIN; -- ADD fct_out := a_ext + b_ext + carry_ext; -- Assign to signal for use outside process pre_D <= fct_out; -- Calculate overflow bit if (a_ext(N-1) = b_ext(N-1) and fct_out(N-1) = not a_ext(N-1)) then pre_OV <= '1'; else pre_OV <= '0'; end if; end process ARITHMETIC_Process; -- Assign the outputs D <= pre_D(N-1 downto 0); -- Assign flags COUT <= pre_D(N); end rtl;