LAB 11: The Camera

Now all submodules must be merged into one design, the complete camera controller. So all modules have to be connected on a new level of hierarchy. This is called structural modelling. Structural modelling means the use (instantiation) and wiring of components resulting in a net list. VHDL provides the following means for structural modelling:

• Component declaration
• Component instantiation
• Component configuration

Before you can use an object in VHDL you have to declare it. As in VHDL’87 only components can be instantiated these have to be declared first. This is done in the declarative part of an architecture or within a package which then has to be referenced.

The actual instantiation is the integration and wiring of the component. The component configuration determines which entity has to be used for a specific component instantiation. If the name of the component instantiated and the name of the entity to be used are identical (mandatory for synthesis!) then no specific component configuration has to be given.

The interface of the top module is shown in the following picture:

TODO Bild The interface of the top module

• Create the new VHDL file.
• Write a testbench to verify the design. Use assertions to check the exposure times during the simulation run.
• Compile and simulate the design.
• Compare the number of Flip Flops that you would expect with the synthesis result.

CAMERA.VHD

library ieee;
use ieee.std_logic_1164.all;
use work.P_DISPLAY.all;
 
entity CAMERA is
  port(CLK         : in std_ulogic;
       RESET       : in std_ulogic;
       TRIGGER     : in std_ulogic;
       SWITCH      : in std_ulogic;
       KEYPAD      : in std_ulogic_vector(9 downto 0);
       MOTOR_READY : in std_ulogic;
       EXPOSE      : buffer std_ulogic;
       DISPLAY     : out T_DISPLAY);
end CAMERA;
 
architecture STRUCT of CAMERA is
  -- Camera components:
  -- DISP_DRV
  -- DECODER
  -- EXP_FF
  -- DISP_CTRL
  -- MOTOR_TIMER
  -- EXP_CTRL
  -- MAIN_CTRL
 
  -- All signals that are not present on the camera entity must be
  -- declared as internal signals
 
begin
  -- Instantiation of the components
  U_DECODER : DECODER
    port map(
      KEYPAD => KEYPAD,
      KEY    => W_KEY);
end STRUCT;
 
configuration CFG_CAMERA of CAMERA is
  for STRUCT
    -- The case-based architecture shall be selected for the DECODER
  end for;
end CFG_CAMERA;