File declarations

file identifier_list : subtype_indication [ file_open_information ] ;

• entity_declarative_part
• architecture_declarative_part
• package
• package_body
• block_declarative_part
• function_declarative_part
• procedure_declarative_part
• process_declarative_part

identifier {, identifier }

[ resolution_function_ name ] type_mark [ constraint ]

[ open file_open_kind_ expression ] is file_logical_name

File declarations are incompatible between VHDL'87 and VHDL'93!

The standard does not define what happens if more than one logical files access the same physical file, specifically for different access modes.

simulation_output is declared as a (virtual) output file of the type my_file_type with the physical path and name /home/usr2/sim.res.

FILE simulation_output : my_file_type IS OUT "/home/usr2/sim.res" ;

rom_content is declared as a (virtual) input file of the type rom_file_type with the physical name “rom2048.txt”.

FILE rom_content : rom_file_type IS IN "rom2048.txt" ;

input and output are predefined files of the type text with the physical names std_input and std_output.

FILE input : text IS IN "std_input";
FILE output : text IS OUT "std_output";

sim_output is declared as a (virtual) output file (mode IN is default) of the type my_file_type with the physical path and name /home/usr3/sim.trc.

FILE sim_output : my_file_type IS OUT "/home/usr3/sim.trc" ;

nowhere is declared as (virtual) file of type my_file_type but without explicitly open it.

FILE nowhere : my_file_type ;

simulation_input is declared as (virtual) file of type my_file_type with the physical path and name /home/usr2/sim.in. At Elaboration, FILE_OPEN(simulation_input, “/home/usr2/sim.res”) is called implicit with the default READ-MODE.

FILE simulation_input : my_file_type IS "/home/usr2/sim.res" ;

simulation_output is declared as (virtual) output file of type my_file_type with the physical path and name /home/usr2/sim.res.

FILE simulation_output : my_file_type OPEN WRITE_MODE IS "/home/usr2/sim.res" ;