vhdl_reference_93:case

CASE

case expression is
     case_statement_alternative
     { case_statement_alternative }
end case [ case_label ] ;
  • function_statement_part
  • procedure_statement_part
  • process_statement_part
  • relation { and relation }
  • relation { or relation }
  • relation { xor relation }
  • relation [ nand relation ]
  • relation [ nor relation ]
  • relation { xnor relation }

The value of bit a is checked. If it is 0 then s is assigned the value 0000 after 2 ns, otherwise it is assigned the value 1111 , also after 2 ns.

CASE a IS
   WHEN '0' => s <= "0000" AFTER 2 ns ;
   WHEN '1' => s <= "1111" AFTER 2 ns ;
END CASE ;

The value of the integer int_value is checked. If it is 0 then int is assigned the value 5 ; if it is 1 , 2 or 8 int is assigned the value of int_value ; if it is between 3 and 7 int is assigned the value int_value + 5 ; if it is 9 no action is carried out. For all other values of int_value int is assigned the value 0 .

CASE int_value IS
   WHEN 0       => int := 5 ;
   WHEN 1 | 2 | 8 => int := int_value ;
   WHEN 3 TO 7  => int := int_value+5;
   WHEN 9       => NULL ;
   WHEN OTHERS    => int := 0 ;
END CASE ;

Depending on the value of the expression two_bit '( a_enable & b_enable ), s is assigned the corresponding value after a certain delay.

CASE two_bit'( a_enable & b_enable ) IS
   WHEN "00" => s <= zero AFTER 1 ns ;
   WHEN "10" => s <= a AFTER 1 ns ;
   WHEN "01" => s <= b AFTER 2 ns ;
   WHEN "11" => s <= one AFTER 1 ns ;
END CASE ;