Content

 

1. VHDL - Overview and Application Field
1.1 Application of HDLs (1)
1.1.1 Application of HDLs (2)
1.1.2 Range of Use
1.2 VHDL - Overview
1.2.1 VHDL - History
1.2.2 VHDL - Application Field
1.2.3 ASIC Development
1.3 Concepts of VHDL
1.3.1 Abstraction
1.3.2 Abstraction Levels in IC Design
1.3.3 Abstraction levels and VHDL
1.3.4 Description of Abstraction Levels
1.3.5 Behavioural Description in VHDL
1.3.6 RT Level in VHDL
1.3.7 Gate Level in VHDL
1.3.8 Information Content of Abstraction Levels
1.4 Modularity and Hierarchy
1.5 Summary
2. VHDL Language and Syntax
2.1 General
2.1.1 Identifier
2.1.2 Naming Convention
2.2 VHDL Structural Elements
2.2.1 Declaration of VHDL Objects
2.2.2 Entity
2.2.3 Architecture
2.2.4 Architecture Structure
2.2.5 Entity Port Modes
2.2.6 Hierarchical Model Layout
2.2.7 Component Declaration
2.2.8 Component Instantiation
2.2.9 Component Instantiation: Named Signal Asscociation
2.2.10 Configuration
2.2.11 Configuration: Task and Application
2.2.12 Configuration: Example (1)
2.2.13 Configuration: Example (2)
2.2.14 Process
2.2.15 VHDL Communication Model
2.2.16 Signals
2.2.17 Package
2.2.18 Library
2.2.19 Design Structure: Example
2.2.20 Sequence of Compilation
2.2.21 Outlook: Testbench
2.2.22 Simple Testbench Example
2.2.23 Summary
2.2.24 Questions
2.2.25 Questions
2.2.26 Questions
2.3 Data Types
2.3.1 Standard Data Types
2.3.2 Datatype 'time'
2.3.3 Definition of Arrays
2.3.4 'integer' and 'bit' Types
2.3.5 Assignments with Array Types
2.3.6 Types of Assignment for 'bit' Data Types
2.3.7 Concatenation
2.3.8 Aggregates
2.3.9 Slices of Arrays
2.3.10 Questions
2.3.11 Questions
2.4 Extended Data Types
2.4.1 Type Classification
2.4.2 Enumeration Types
2.4.3 Enumeration Types - Example
2.4.4 BIT Type Issues
2.4.5 Multi-valued Types
2.4.6 IEEE Standard Logic Type
2.4.7 Resolved and Unresolved Types
2.4.8 Std_Logic_1164 Package
2.4.9 Resolution Function
2.4.10 STD_LOGIC vs STD_ULOGIC
2.4.11 The NUMERIC_STD Package
2.4.12 Arrays
2.4.13 Multidimensional Arrays
2.4.14 Aggregates and Multidimensional Arrays
2.4.15 Records
2.4.16 Type Conversion
2.4.17 Subtypes
2.4.18 Aliases
2.5 Operators
2.5.1 Logical Operators
2.5.2 Logical Operations with Arrays
2.5.3 Shift Operators: Examples
2.5.4 Relational Operators
2.5.5 Comparison Operations with Arrays
2.5.6 Arithmetic Operators
2.5.7 Questions
2.5.8 Questions
2.6 Sequential Statements
2.6.1 IF Statement
2.6.2 IF Statement: Example
2.6.3 CASE Statement
2.6.4 CASE Statement: Example
2.6.5 Defining Ranges
2.6.6 FOR Loops
2.6.7 Loop Syntax
2.6.8 Loop Examples
2.6.9 WAIT Statement
2.6.10 WAIT Statement: Examples
2.6.11 WAIT Statements and Behavioural Modeling
2.6.12 Variables
2.6.13 Variables vs. Signals
2.6.14 Use of Variables
2.6.15 Variables: Example
2.6.16 Global Variables (VHDL'93)
2.7 Concurrent Statements
2.7.1 Conditional Signal Assignment
2.7.2 Conditional Signal Assignment: Example
2.7.3 Selected Signal Assignment
2.7.4 Selected Signal Assignment: Example
2.7.5 Concurrent Statements: Summary
2.8 RTL-Style
2.8.1 Combinational Process: Sensitivity List
2.8.2 WAIT Statement <-> Sensitivity List
2.8.3 Combinational Process: Incomplete Assignments
2.8.4 Combinational Process: Rules
2.8.5 Clocked Process: Clock Edge Detection
2.8.6 Detection of a Rising Edge by Use of Functions
2.8.7 Register Inference
2.8.8 Asynchronous Set/Reset
2.8.9 Clocked Process: Rules
2.8.10 Questions
2.8.11 Questions
2.8.12 Questions
2.9 Subprograms
2.9.1 Parameters and Modes
2.9.2 Functions
2.9.3 Procedures
2.10 Subprogram Declaration and Overloading
2.10.1 Overloading Example
2.10.2 Overloading - Illegal Redeclarations
2.10.3 Overloading - Ambiguity
2.10.4 Operator Overloading
2.10.5 Operator Overloading - Example
2.10.6 Questions
3. Simulation
3.1 Sequence of Compilation
Example
Changes in ... recompile files ...
3.2 Simulation Flow
3.2.1 Elaboration
3.2.2 Initialization
3.2.3 Execution
3.3 Process Execution
3.3.1 Concurrent versus Sequential Execution
3.3.2 Signal Update
3.3.3 Delta Cycles (1)
3.3.4 Delta Cycles (2)
3.3.5 Delta Cycles - Example
3.3.6 Process Behaviour
3.3.7 Postponed Processes
3.4 Delay Models
3.4.1 Projected Output Waveforms (LRM)
3.4.2 Transport Delay (1)
3.4.3 Transport Delay (2)
3.4.4 Inertial Delay (1)
3.4.5 Inertial Delay (2)
3.4.6 Inertial Delay (3)
3.5 Testbenches
3.5.1 Structure of a VHDL Testbench
3.5.2 Example
Clock and Reset Generation
Stimuli Generation
Response Analysis
3.6 File I/O
3.6.1 Example for File I/O (1/4)
Example (2/4)
Example (3/4)
Example (4/4)
4. Synthesis
4.1 What is Synthesis?
4.1.1 Synthesizability
4.1.2 Different Language Support for Synthesis
4.1.3 How to Do?
4.1.4 Essential Information for Synthesis
4.1.5 Synthesis Process in Practice
4.1.6 Problems with Synthesis Tools
4.1.7 Synthesis Strategy
4.2 RTL-style
4.2.1 Combinatorics
4.2.2 Complete sensitivity lists
4.2.3 WAIT statement <-> Sensitivity List
4.2.4 Incomplete assignments
4.2.5 Rules for synthesizing combinational logic
4.2.6 Modelling of Flip Flops
4.2.7 Description of a rising clock edge for synthesis
4.2.8 Describing a rising clock edge by means of a function call
4.2.9 Counter synthesis
4.2.10 FF with asynchronous reset
4.2.11 Rules for clocked processes
4.2.12 Questions
4.2.13 Questions
4.2.14 Questions
4.3 Combinational Logic
4.3.1 Coding Style Influence
4.3.2 Source Code Optimization
4.3.3 IF structure <-> CASE structure
4.3.4 Implementation of a Data Bus
Problems with Internal Bus Structures
Portable and Safe Bus Structure
4.3.5 Example of a Multiplier
Multiplier Function Table
Multiplier Minterms -- Karnaugh Diagram
Multiplier: VHDL Code using the Function Table
Multiplier: Minterm Conversion
Multiplier: Integer Realization
4.3.6 Synthesis of Operators
Synthesis Results
4.3.7 Example of an Adder
4.4 Sequential Logic
4.4.1 RTL - Combinational Logic and Registers
4.4.2 Variables in Clocked Processes
Example
4.5 Finite State Machines and VHDL
4.5.1 One "State" Process
4.5.2 Two "State" Processes
4.5.3 How Many Processes?
4.5.4 State Encoding
4.5.5 Extension of Case Statement
4.5.6 Extension of Type Declaration
4.5.7 Hand Coding
4.5.8 FSM: Medvedev
4.5.9 Medvedev Example
4.5.10 Waveform Medvedev Example
4.5.11 FSM: Moore
4.5.12 Moore Example
4.5.13 Waveform Moore Example
4.5.14 FSM: Mealy
4.5.15 Mealy Example
4.5.16 Waveform Mealy Example
4.5.17 Modelling Aspects
4.5.18 Registered Output
4.5.19 Registered Output Example (1)
4.5.20 Waveform Registered Output Example (1)
4.5.21 Registered Output Example (2)
4.5.22 Waveform Registered Output Example (2)
4.6 Advanced Synthesis
4.6.1 Parameterization via Constants
4.6.2 Parameterization via Generics(1)
4.6.3 Parameterization via Generics(2)
4.6.4 GENERATE Statement
4.6.5 Conditional GENERATE Statement
4.6.6 'Parameterization' via Signals
5. Project Management
5.1 Design Components
5.1.1 Libraries
5.1.2 The LIBRARY Statement
5.1.3 The USE Statement
5.2 Name Spaces
5.3 File Organisation
5.3.1 Packages
5.3.2 Package Syntax
5.3.3 Package Example
5.3.4 Use of Packages
5.3.5 Visibility of Package Contents