A testbench is used to verify the specified functionality of a design. It provides the stimuli for the Device Under Test (DUT) and analyses the DUT's respones or stores them in a file. Information necessary for generating the stimuli can be integrated directly in the testbench or can be loaded from an external file. Simulation tools visualize signals by means of a waveform which the designer compares with the expected response. In case the waveform does not match the expected response, the designer has to correct the source code. When dealing with bigger designs, this way of verification proofs impractical and will likely become a source of errors. The only way out would be a widely automated verification, but this is still a dream for the future.