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...	Synthesizeable VHDL-Model-Library		...
	Copyright:	University of Patras    Dept. of Electrical and Computer Engineering    Prof. Ph.D. C. Goutis    Patras, 26110 Greece    Tel.: +30-61-997340    Fax: +30-61-994798    Email: goutis@ee.upatras.gr    W3: http://www.vlsi.ee.upatras.gr/Goutis\goutis.html
		The modules are implemented as parameterizeable VHDL models    and Testbenches. By selecting the corresponding link you    receive the VHDL description of the module or the testbench.    After marking the VHDL source code and copying it to a local    text file, you just have to insert the appropriate values for    the generics in the entities or component instantiations.    Here you find a package with useful functions.    Content: ALUs : Various Arithmetic and Logical Units COMPARATORs : Equality and Magnitude Comparators COUNTERs : Up-Down, Binary-Gray Counters ENC_DEC : Encoders and Decoders FIFOs : Single and Dual Clocked FIFOS INC_DECRs : Incrementers and Decrementers MUXERs : Various width Multiplexers REGISTERs : Register Files SHIFTERs : Left, Right and Bidirectional Shifters with various Input-Output Options SPECIAL : Various Models that Perform special functions UNIVERSAL MULTIPLIER : A universal multiplier that implements the multiplication in all arithmetic number systems (i.e. unsigned.signed-magnitude, 1's complement and 2's complement) FIR : An unrolled implementation of an FIR (Finite Impulse Response) filter. The multiplications are implemented using shift-add operations.
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