VHDL-ONLINE Main (content)

University of Erlangen-Nürnberg

Institute for Computer Aided Circuit Design

Prof. Dr.-Ing. W. H. Glauert

(Best look with NETSCAPE . . . Enable JAVA and JAVASCRIPT)

Guestbook
Server statistics...
VHDL-Online Server-Search-Engine:

Keyword-Search inside all the server documents.
Displaying results as links or as excerpt (the first 5 lines).

VHDL-Tutorial:(we use frames and javascript!)

First steps with VHDL. Introduction in simulation and synthesis of integrated circuits using VHDL.
Online-Lectures with multiple-choice exercises.

VHDL-FSM-Tutorial:(we use frames and javascript!)

Modelling of Finite-State-Machines: Moore, Mealy, Medvedev
Different modelling views and examples.
Simulation and synthesis aspects.

VHDL-Glossary

All the VHDL keywords from A to Z.

VHDL'93 Language-Reference:

All the language constructs with many examples and explanations.
The VHDL language-constructs are displayed tabularly.
In the table center the BNF of the VHDL construct is shown.
In the table cells arround the center, the place where the constructs can be used is coloured red.
We have the BNF93, but the examples are still BNF87...we work on it ...
...or you send us '93 examples, we can insert.

VHDL-Workshop-Camera:

Design of a digital camera with counters, multiplexors and statemachines.
You can use the tools of SYNOPSYS and ALTERA via the internet.
Please register here.

FPGA-Online:(in Siegen)

Currently Down

Workshop about FPGAs, based upon the solutions of the VHDL-workshop.
Remote access to the XILINX tools possible. Register in Siegen.

Tutorial with VISUAL-HDL (in Siegen)

Currently Down

Introduction in VISUAL-HDL (Summit)
Remote access to the Summit tools possible. Register in Siegen.

VHDL-Entwurfssichten:(in Bremen, in German)

Currently Down

Workshop über verschiedene, grundlegende Modellierungsmöglichkeiten.
Zugriff auf die Werkzeuge von Synopsys. Registrierung in Bremen.

Design-Workshop with SpeedCHART

The same design like in the VHDL-Workshop-Camera using SpeedChart for all parts.
Up to now, it is not possible to use SpeedChart via internet.

VHDL-Modell-Bibliothek: (in German)

Parameterizeable VHDL models with testbench.
Synthesizeable!!! (designed with SYNOPSYS)
You send us the parameters, we send you the VHDL file.
....we work on it

VHDL-Modell-Bibliothek aus Patras
- You insert your VHDL model, we give you a testbench template
VHDL-Chat

Multi-User Talk session, based upon JAVA applets

CD-ROM order now (in English and German)