courses:system_design:vhdl_vs_verilog:history_of_verilog_systemverilog

History of Verilog, SystemVerilog

For completeness' sake

  • invented 1984 as proprietary hardware modeling and simulation language
  • purchased by Cadence in 1990, transferred into public domain
  • became IEEE Std. 1364-1995 (aka. Verilog-95)
  • extensions of Verilog-95 became IEEE Standard 1364-2001 (Verilog-2001) - still the dominant flavor of Verilog supported by most EDA tools
  • Verilog 2005 (IEEE Std. 1364-2005): minor corrections, few new features
  • Verilog-AMS: attempts to integrate analog and mixed signal modelling with traditional Verilog, separate part of Verilog standard
  • SystemVerilog (IEEE Std. P1800-2005): superset of Verilog-2005 with many new features and capabilities to aid design-verification and -modelling
  • 2009: SystemVerilog and Verilog standards merged into SystemVerilog 2009 (IEEE Standard 1800-2009) - i.e. a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog

Notes

  • Cadence transferred Verilog into the public domain under the Open Verilog International (OVI) (now known as Accellera) organization.
  • SystemVerilog started with the donation of the Superlog language (Co-Design Automation) to Accellera in 2002.[1] The bulk of the verification functionality is based on the OpenVera language donated by Synopsys.
  • The feature-set of SystemVerilog can be divided into two distinct roles:
    1. SystemVerilog for RTL design is an extension of Verilog-2005; all features of that language are available in SystemVerilog.
    2. SystemVerilog for verification uses extensive object-oriented programming techniques and is more closely related to Java than Verilog.

Chapters of System Design > VHDL vs. Verilog