Differences between VHDL and Verilog
Comparison VHDL vs. Verilog
| VHDL | Verilog (2001) | |
|---|---|---|
| Concept / Syntax from: | Ada, not cAse-SensItive | C language, case-sensitive |
| Strong typing | Yes (restrictive types) | No (e.g. implicit conversations) |
| User-defined, physical, enumeration or pointer types | Yes. 9-valued logic | No. 4-valued logic |
| All-read sensitivity | No (VHDL-93), Yes (VHDL-2008): process(all) | Yes: @(*) |
| Other hierarchy | Yes: separate entity / arch. | No |
| Gate level modeling | VITAL. Very good FPGA library support. | Builtin primitives. UDPs. Better availability of ASIC lib. support |
| Assertions | Partial (combinatorial) | No |
| Conditional statements | if-then-else/elsif, CSA (priority) case, SSA (mux) | if-else (priority), ?: (cond.in csa) case, casex (mux) |
| Named events | No | Yes |
| Interface abstraction | Partial (comp., 2-layer binding) | No |
| Separate packaging | YES: Packages | YES: Include Files |
Notes
Wikipedia: a type system is said to feature strong typing when it specifies one or more restrictions on how operations involving values of different data types can be intermixed. The opposite of strong typing is weak typing.
Most generally, “strong typing” implies that the programming language places severe restrictions on the intermixing that is permitted to occur, preventing the compiling or running of source code which uses data in what is considered to be an invalid way. For instance, an addition operation may not be used with an integer and string values; a procedure which operates upon linked lists may not be used upon numbers. However, the nature and strength of these restrictions is highly variable.
Focus of VHDL and Verilog
| VHDL | Verilog (2001) | |
|---|---|---|
| roots, typing | derived from ADA, strong and richly typed: bugs easily found during analysis/compilation, but limits performance, type conversion functions have to be used | derived from C and Hilo (old HDL), weakly and limited typed: bugs may be discovered first during runtime |
| focus | safe language, focus to catch as many errors as possible early | language focussed on writing models quickly |
| high-level modeling | many constructs and features for HL modeling: packages, libraries, configu-rations, generate & generic statements | no equivalent high-level modeling state-ments in Verilog (except to parameterize models by overloading constants) |
| verbosity | verbose language requirements: inten-ded to make designs self-documenting | compact, lack of packaging capabilities, difficult to develop new, reusable functions |
| ambiguity | emphazised on unambiguos semantics and easily portable designs from one tools to the next, no race conditions | more ambigous simulation semantics, can result in race conditions, different results on different vendor tools/releases possible |
| sim. control | no simulation control and monitoring defined in language | basic simulation control capabilities |
Chapters of System Design > VHDL vs. Verilog