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courses:system_design:vhdl_language_and_syntax:vhdl_structural_elements:quiz

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Quiz

An architecture...

...can exist on its own
...can exist only together with its dedicated design entity.
...contains a description of the module's behavior.

In VHDL, sequential statements...

...are defined in the architecture
...are defined in the process

The configuration...

...generates the simulateable object.
...is declared within the architecture.
...chooses the entity for a certain architecture.

The component declaration...

...integrates a certain entity into a preset socket.
...defines only the socket type.
...should have the same name as the dedicated entity for default-configuration.

Component instantiation...

...generates the socket of the component type.
...wires the socket (=component) to the PCB (=entity).

Concurrent statement...

...are declared only in the architecture.
...are declared only in subprograms.
...are executed consecutively.

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Chapters of System Design > VHDL Language and Syntax > VHDL Structural Elements

VHDL Structural Elements
Entity and Architecture
Component
Configuration
Process
Package and Library
Outlook and Summary
Quiz

Chapters of System Design > VHDL Language and Syntax

General Issues
VHDL Structural Elements
Data Types
Process Execution
Extended Data Types
Operators
Sequential Statements
Subprograms
Subprogram Declaration and Overloading
Concurrent Statements

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