courses:system_design:vhdl_language_and_syntax:vhdl_structural_elements:process

Process

Introduction

entity AND_OR_XOR is
  port(A, B        : in bit;
       Z_OR, Z_AND : out bit;
       Z_XOR       : out bit);
end AND_OR_XOR;
 
architecture RTL of AND_OR_XOR is
begin
  A_O_X: process (A,B) -- sensitivity list
  begin
    Z_OR  <= A or B;
    Z_AND <= A and B;
    Z_XOR <= A xor B;
  end process A_O_X;
 
end RTL;
  • Contains sequentially executed statements
  • Exist within an architecture, only
  • Several processes run concurrently
  • Execution is controlled either via
    • sensitivity list (contains trigger signals), or
    • wait-statements
  • The process label is optional

Notes

Because the statements within an architecture operate concurrently another VHDL construct is necessary to achieve sequential behavior. A process, as a whole, is treated concurrently like any other statement in an architecture and contains statements that are executed one after another like in conventional programming languages. In fact it is possible to use the process statement as the only concurrent VHDL statement.

The execution of a process is triggered by events. Either the possible event sources are listed in the sensitivity list or explicit wait statements are used to control the flow of execution. These two options are mutually exclusive, i.e. no wait statements are allowed in a process with sensitivity list. While the sensitivity list is usually ignored by synthesis tools, a VHDL simulator will invoke the process code whenever the value of at least one of the listed signals changes.

Consequently, all signals that are read in a purely combinational process, i.e. that influence the behavior, have to be mentioned in the sensitivity list if the simulation is to produce the same results as the synthesized hardware. Of course the same is true for clocked processes, yet new register values are to be calculated with every active clock edge, only. Therefore the sensitivity list contains the clock signal and asynchronous control signals (e.g. reset).

A process statement starts with an optional label and a ’:’ symbol, followed by the ’process’ keyword. The sensitivity list is also optional and is enclosed in a ’(’ ’)’ pair. Similar to the architecture statement, a declarative part exists between the header code and the keyword ’begin’. The sequential statements are enclosed between ’begin’ and ’end process’. The keyword ’process’ has to be repeated! If a label was chosen for the process, it has to be repeated in the end statement, as well.

VHDL Communication Model

VHDL Communication Model

  • Processes are concurrent statements
  • Several processes
    • run parallel
    • linked by signals in the sensitivity list
    • sequential execution of statements
  • Link to processes of other entity/architecture pairs via entity interface

Notes

Process statements are concurrent statements while the instructions within each process are executed sequentially, i.e. one after another. All processes of a VHDL design run in parallel, no matter in which entity or hierarchy level they are located. They communicate with each other via signals. These signals need to be ports of the entities if processes from different architectures depend from another.

Signals

Signals

  • Every signal has a specific data type
    • number of possible values
  • Predefined data types
    • bit, bit_vector, integer. real, …
  • User defined data types
    • more accurate hardware model
    • enhanced readability
    • improved error detection

Notes

Each signal has a predetermined data type which limits the amount of possible values for this signal. Synthesizable data types offer only a limited number of values, i.e. it is possible to map these values to a certain number of wires. Only the most basic data types are already predefined in VHDL, like bit, bit vectors and integer.

The user can define his own data types which might become necessary to enhance the accuracy of the model (tristate drivers, for example, may be set to high impedance instead of a low or high voltage level), for better readability (e.g. a signal value called “IDLE” tells more about its function than “00101”or “17”) and to allow for automatic error detection (e.g. by restricting the range of legal values).

Chapters of System Design > VHDL Language and Syntax > VHDL Structural Elements

Chapters of System Design > VHDL Language and Syntax