courses:system_design:vhdl_language_and_syntax:vhdl_structural_elements:configuration

Configuration

Configuration: Introduction

Configuration 

entity HALFADDER is
  port(A, B       : in bit;
       SUM, CARRY : out bit);
end HALFADDER;
...
  component HALFADDER
    port(A, B       : in bit;
         SUM, CARRY : out bit);
   end HALFADDER;
  signal W_SUM : bit;
  signal W_CARRY1, W_CARRY2:
bit;
...
  MODULE1: HALFADDER
    port map(A, B, W_SUM, W_CARRY1);
VHDL’93: Entities may be instantiates directly without a preceding component declaration

Notes

Component declaration and instantiation are independent of VHDL models that are actually available. It is the task of the VHDL configuration to link the components to entity/architecture pairs in order to build the complete design. In summary: A component declaration provides a certain kind of socket that can be placed on the circuit as often as necessary with component instantiations. The actual insertion of a device into the instantiated sockets is done by the configuration.

In VHDL’93 it is possible to omit the component declaration and to instantiate entities directly (see examples of 9.6 Component instantiation in the reference).

Configuration: Task and Application

Configuration Application 

entity FULLADDER is
...
end FULLADDER;
architecture STRUCT of FULLADDER is
...
end STRUCT;
 
configuration CFG_FULLADDER of
                  FULLADDER is
  for STRUCT
   -- select architecture STRUCT
   -- use default configuration rules
  end for;
end configuration CFG_FULLADDER;
  • Selects architecture for top-level entity
  • Selects entity/architecture pairs for instantiated components
  • Generates the hierarchy
  • Creates a simulatable object
  • Default binding rules:
    • selects entity with same name as component
    • signals are associated by name
    • last compiled architecture is used
VHDL’93: The keyword ‘configuration’ may be repeated after the keyword ‘end’

Notes

The connection between the entity and the architecture that is supposed to be used for the current simulation is established in the configuration, i.e. it creates the final design hierarchy. This includes the selection of the architecture for the top-level entity. The configuration is the only VHDL object that can be simulated or synthesized. While it is possible to control the configuration process manually for simulation purposes, synthesis tools always apply the default rule set.

For this to succeed, the component names have to match the names of existing entities. Additionally, the port names, modes and data types have to coincide - the order of the ports in the component declaration is ignored. The most recently analysed architecture for the specific entity will be selected as corresponding architecture.

The example shows the default configuration for a structural architecture. Some simulators require an explicit configuration definition of this kind the top-level entity. A configuration refers to a specific entity, which is FULLADDER in this case. The architecture STRUCT is selected with the first ’for’ statement. As no additional configuration commands are given, the default rules apply for all other components.

Configuration: Example (1)

entity HA1 is
  port(A, B       : in bit;
       SUM, CARRY : out bit);
end HA1;
architecture RTL of HA1 is
...
end RTL;
entity HA2 is
  port(U, V    : in bit;
       X, Y    : out bit);
end HA2;
architecture GATE of HA2 is
...
end GATE;
entity FULLADDER is
  port(A, B, CARRY_IN : in bit;
       SUM, CARRY     : out bit);
end FULLADDER;
 
 architecture STRUCT of FULLADDER is
   component HALFADDER
    port(A, B       : in bit;
         SUM, CARRY : out bit);
  ...
   signal W_SUM, W_CARRY1, W_CARRY2: bit;
 
begin
 MODULE1: HALFADDER
   port map (A, B, W_SUM, W_CARRY1);
 
 MODULE2: HALFADDER
   port map(W_SUM, CARRY_IN, SUM, W_CARRY2);
...
 
end STRUCT;

Notes

Please have a look at the VHDL code fragments in order to understand a more elaborated configuration example:

  • In the end, a fulladder shall be simulated again. The structure of this fulladder is the same as in the example before, i.e. two halfadders are used. Each halfadder is declared to have two signals of data type ’bit’ as input and output, respectively. The component ports are connected to the architecture’s signals by position, i.e. the first signal is connected to the first port.
  • An entity named HALFADDER shall not be available, however, and the two entities HA1 and HA2 that also have different architectures named RTL and GATE, respectively are to be used. Both entities match the ports from the component declaration.

Configuration: Example (2)

configuration CFG_FULLADDER of
FULLADDER is
  for STRUCT
    for MODULE2: HALFADDER
       use entity work.HA2(GATE);
        port map (U => A,
                  V => B,
                  X => SUM,
                  Y => CARRY);
    end for;
 
    for others: HALFADDER
       use entity work.HA1(RTL);
    end for;
  end for;
end CFG_FULLADDER;
  • Entity/architecture pairs may be selected by use of
    • instance names
    • ‘all’: all instances of the specified component
    • ‘others’: all instances not explicitly mentioned
  • If the Port names differ ⇒ port map clause
  • Possible to reference an existing configuration of a submodule

Notes

Again, the architecture STRUCT is selected for the FULLADDER entity. Within this for loop, however, the entities and architectures for the subordinated components are selected.

For this, the for statement is used again. The first name after the keyword ’for’ names the component instantiation, followed by a ’:’ and the component name. The keyword ’all’ can be used, if all instances of a component shall be addressed. Within the for loop, the use statement selects the entity by specifying the absolute path to that object. Unless explicitly changed, all VHDL objects are compiled into the library work. The architecture for the selected entity is enclosed in a ’(’ ’)’ pair.

As the port names of the entity HA2 do not match the port names from the component declaration a port map statement is necessary again. Again, it is possible to map the names by positional association, yet an explicit names association should always be used to enhance readability. In this case, the formal parameters are the port names of the entity, while the component port names are used as actuals.

It is also possible to address all those components that have not been configured yet with the keyword ’others’. This is necessary in this case as there does not exist an entity named HALFADDER. Instead, the entity A and the corresponding architecture RTL is used for all HALFADDER instantiations other than MODULE2. A port map clause is not necessary as the entity port names are equivalent to the names of the component.

All other components that might exist are treated according to the default configuration rules.

In order to simplify the hierarchy definition of large designs it is often useful to define the configuration for the submodules and to reference these configurations from the top level.

Chapters of System Design > VHDL Language and Syntax > VHDL Structural Elements

Chapters of System Design > VHDL Language and Syntax