courses:system_design:vhdl_language_and_syntax:vhdl_structural_elements:component

Component

Hierarchical Model Layout

Full Adder

Full adder: 2 halfadders + 1 OR-gate

Notes

VHDL allows for a hierarchical model layout, which means that a module can be assembled out of several submodules. The connections between these submodules are defined within the architecture of a top module. As you can see, a fulladder can be built with the help of two halfadders (module1, module2) and an OR gate (module3).

A purely structural architecture does not describe any functionality and contains just a list of components, their instantiation and the definition of their interconnections.

Component Declaration

entity FULLADDER is
  port (A,B, CARRY_IN : in bit;
        SUM, CARRY    : out bit);
end FULLADDER;
 
architecture STRUCT of FULLADDER is
  signal W_SUM : bit;
  signal W_CARRY1, W_CARRY2 : bit;
 
  component HALFADDER
    port (A, B       : in bit;
          SUM, CARRY : out bit);
  end component;
 
  component ORGATE
    port (A, B : in bit;
          RES : out bit);
  end component;
 
begin
...
  • In declarative part of the architecture
  • Comparable to a ‘socket’-type
The component port list does not replace the declaration of connecting signals (local objects, only)

Notes

The entity of the fulladder can be derived directly from the block diagram. The inputs A and B, as well as a CARRY_IN input are required, together with the SUM and the CARRY signals that serve as outputs.

As the fulladder consists of several submodules, they have to be “introduced” first. In a component declaration all module types which will be used, are declared. This declaration has to occur before the ’begin’ keyword of the architecture statement. Note, that just the interface of the modules is given here and their use still remains unspecified. The component declaration is therefore comparable with a socket definition, which can be used once or several times and into which the appropriate entity is inserted later on. The port list elements of the component are called local elements, which means that they are not signals!

In this case, only two different sockets, namely the socket HALFADDER and the socket ORGATE are needed. Arbitrary names may be chosen for the components, yet it is advisable to use the name of the entity that will be used later on. Additionally, the port declaration should also be identical. This is absolutely necessary, when the design is to be synthesized, as the software ignores VHDL configuration statements and applies the default rules.

Component Instantiation

architecture STRUCT of FULLADDER is
  component HALFADDER
    port (A, B       : in  bit;
          SUM, CARRY : out bit);
  end component;
 
  component ORGATE
    port (A, B : in  bit;
          RES  : out bit);
  end component;
  signal W_SUM, W_CARRY1, W_CARRY2 : bit;
 
begin
 
  MODULE1 : HALFADDER
    port map(A, B, W_SUM, W_CARRY1);
 
  MODULE2 : HALFADDER
    port map (W_SUM, CARRY_IN,
              SUM, W_CARRY2);
 
  MODULE3 : ORGATE
    port map (W_CARRY2, W_CARRY1, CARRY);
 
end STRUCT;
  • Socket generation
  • How many do I need?
  • Instantiation in definition part of architecture (after ‘begin’)
  • Places socket on PCB
  • Wires signals:
    • default: positional association

Notes

If a component has been declared, that means the socket type is fixed, it can be used as often as necessary. This is done in form of component instantiations, where the actual socket is generated. This is comparable to the placement of sockets on a printed circuit board (PCB). The entity/architecture pair that provides the functionality of the component is inserted into the socket at a later time when the configuration of a VHDL design is built.

Each component instance is given a unique name (label) by the designer, together with the name of the component itself. Component instantiations occur in the definition part of an architecture (after the keyword ’begin’). The choice of components is restricted to those that are already declared, either in the declarative part of the architecture or in a package.

As the component ports or socket pins have to be connected to the rest of the circuit, a port map statement is necessary. It has to list the names of the architecture signals that shall be used. As default, the so called positional association rules apply, i.e. the first signal of the port map list is connected to the first port from the component declaration, etc.

Component Instantiation: Named Signal Association

entity FULLADDER is
  port (A,B, CARRY_IN : in bit;
        SUM, CARRY    : out bit);
end FULLADDER;
architecture STRUCT of FULLADDER is
  component HALFADDER
    port (A, B       : in bit;
          SUM, CARRY : out bit);
  end component;
  ...
  signal W_SUM : bit;
  signal W_CARRY1, W_CARRY2 : bit;
begin
  MODULE1: HALFADDER
    port map(A     => A,
             SUM   => W_SUM,
             B     => B,
             CARRY => W_CARRY1);
...
end STRUCT;
  • Named association:
    • left side: “formals” (port names from component declaration)
    • right side: “actuals” (architecture signals)
  • Independent of order in component declaration

Notes

Instead of the positional association that was used in the previous example it is also possible to connect architecture signals directly to specific ports. This is done by the so called named association where the order of the signals is not restricted. The port names from the component declaration, also called “formals”, are associated with an arrow ’⇒’ with the signals of the entity (“actuals”).

In the example, the output port SUM is declared third in the component declaration. In the port map statement, however, this port is connected to the signal W_SUM in the second place. Please note that the list elements are separated by ’,’ symbols in the port map statement unlike the ’;’ symbols that are used in port declarations.

Chapters of System Design > VHDL Language and Syntax > VHDL Structural Elements

Chapters of System Design > VHDL Language and Syntax