courses:system_design:vhdl_language_and_syntax:sequential_statements:wait_statement

WAIT Statement

Fundamentals

  • ‘wait’ statement stop the process execution
    • The Process os continued when the instruction is fulfilled
  • Different types of wait statement:
    • wait for a specific time 
      wait for SPECIFIC_TIME;
    • wait for a signal event 
      wait on SIGNAL_LIST;
    • wait for a true condition (requires an event) 
      wait until CONDITION;
    • indefinite (process is never reactivated) 
      wait ;
Wait statements must not be used in processes with sensitivity list

Notes

As mentioned before, processes may be coded in two flavours. If the sensitivity list is omitted, another method will be needed to stop process execution.

Wait statements put the process execution on hold until the specified condition is fulfilled. If no condition is given, the process will never be reactivated again.

Wait statements must not be combined with a sensitivity list, independent from the application field.

WAIT Statement Example

  • Flip flop model
entity FF is                                         
  port(D, CLK : in bit;                              
       Q      : out bit);                               
end FF; 
architecture BEH1 of FF is
begin
  process
  begin
    wait on CLK;
    if (CLK = ‘1’) then
      Q <= D;
    end if;
  end process;
end BEH1;
 
architecture BEH2 of FF is
begin
  process
  begin
    wait until CLK = ‘1’;
 
    Q <= D;
  
  end process;
end BEH2;
  • Testbench: stimuli generation
STIMULUS: process
begin
  SEL    <= ’0’;
  BUS_B  <= "0000";
  BUS_A  <= "1111";
  wait for 10 ns;
  SEL    <= ‘1’;
  wait for 10 ns;
  
  SEL    <= ‘0’;
  wait for 10 ns;
  
 
  wait;
 
end process STIMULUS;
not for synthesis!

Notes

Processes without sensitivity list are executed until a wait statement is reached.

In the example architecture BEH_1 of a flip flop, the execution resumes as soon as an event is detected on the CLK signal (’wait on CLK’).

The following if statement checks the level of the clock signal and a new output value is assigned in case of a rising edge.

In BEH_2, both checks are combined in a single ’wait until’ statement.

The evaluation of the condition is triggered by signal events, i.e. the behavior is the same.

Via ’wait for’ constructs it is very easy to generate simple input patterns for design verification purposes.

WAIT Statements and Behavioral Modelling

WAIT Statements and Behavioral Modelling

  • Timing behavior from specification
  • Translation into VHDL
  • Based on time
READ_CPU : process
begin
  wait until CPU_DATA_VALID = ‘1’;
  CPU_DATA_READ <= ‘1’;
  wait for 20 ns;
  LOCAL_BUFFER <= CPU_DATA;
  wait for 10 ns;
  CPU_DATA_READ <= ‘0’;
end process READ_CPU;

Notes

Wait constructs, in general, are an excellent tool for describing timing specifications.

For example it is easy to implement a bus protocol for simulation.

The timing specification can directly be translated to simulatable VHDL code.

But keep in mind that this behavioral modelling can only be used for simulation purposes as it is definitely not synthesizable.

Chapters of System Design > VHDL Language and Syntax > Sequential Statements

Chapters of System Design > VHDL Language and Syntax