Application Field of HDLs

Notes

VHDL is a hardware description language.

Different descriptions exist for the hardware functionality.

Complex systems are often described by the behavior that is observable from the outside.

• controlling functionality, state machines
• bus protocolls and interfaces

More or less, all this is an abstract description of boolean behavior and boolean equations. This is a very short and precise description.

VHDL covers the complete range of boolean logic applications and can be used to model digital hardware in a general way.

Notes

The most evident application is probably the development of a formal model of the behavior of a system. With formality, misunderstandings and misinterpretations can be avoided. Because of the self documenting character of VHDL, a VHDL model can even serve as system documentation to a certain degree.

The big advantage of hardware description languages is the possibility to actually execute the code. In principle, they are nothing else than a specialized programming language. Coding errors of the formal model or conceptual errors of the system can be found by running simulations. There, the response of the model on stimulation with different input values can be observed and analysed.

During the development cycle the description has to become more and more precise until it is actually possible to manufacture the product. The (automatic) transformation of a less detailed description into a more elaborated one is called synthesis. Existing synthesis tools are capable of mapping specific constructs of hardware description languages directly to the standard components of integrated circuits. This way, a formal model of the hardware system can be used from the early design studies to the final netlist. Software support is available for the necessary refinement steps.

Notes

Additionally, hardware description languages offer so called design reuse capabilities. Similar to simple electronic components, like for example a resistor, the corresponding HDL model can be re-used in several designs/projects. It is common use that frequently needed function blocks (macros) are collected in model libraries. The selection of an existing module is not only restricted to the design engineer but can sometimes be performed by a synthesis tool.

Notes

As stated in the slides before hardware description languages can be used for a broad of application in the process of designing hardware/systems. It can be used on system level to provide HW models in an early design process to already verify the whole system level behaviour against its specification. It can be used to write actual simulation environments for the design in a behavioural level. And of course it is used to actually design hardware om RTL (register transfer level) or/and on a logic level.

Notes

The design process always starts with a specification phase: The component which is to be designed is defined with respect to function, size, interfaces, etc. Despite the complexity of the final product, mainly simple methods, based on paper and pencil most of the time, are being used. After that, self-contained modules have to be defined on the system level. Their interaction is described very precisely and interfaces (inputs, outputs, data formats), clock speed and reset mechanism are specified. With that information at hand, pure simulation models of the circuit can be developed. Behavior models of standard components can be integrated into the system from libraries of commercial model developers. The overall system can already be simulated.

On the logic level, the models that have to be designed are described with all the synthesis aspects in view. As long as only a certain subset of VHDL constructs is used, commercial synthesis programs can derive the boolean functions from this abstract model description and map them to the elements of an ASIC gate library or the configurable logic blocks of FPGAs. The result is a netlist of the circuit or of the module on the gate level.

Finally, the circuit layout for a specific ASIC technology can be created by means of other tools from the netlist description. Every transition to a lower abstraction level must be proven by functional validation. For this purpose, the description is simulated in such a way that for all stimuli (= input signals for the simulation) the module’s responses are compared. VHDL is suitable for the design phases from system level to gate level.