Timing behavior

important for the ASIC Synthesis:

• Input-Setup-Time TSU
• Input-Hold-Time TH
• Output-Delay-Time TOD
• Wire-Delay-Time (spez. Clock Skew)

D stable while

• T_SU before the clock edge and
• T_H after the clock edge

that is all nodes in master part become stable values/levels

Output-Delay-Time: T_OD delay at gate output

Problem: gates are faster (in relation to wires)

T_OD ↓ but T_skew ↑

Static-Timing-Analysis: checking after layout if the sum of all output-delays and real wire-delay-times results in setup/hold-time violations

port (
    RESET   : in std_ulogic;
   CLK      : in std_ulogic;
   Q        : buffer std_logic_vector (3 downto 0)
);

process (CLK)
begin
   if CLK'event and CLK='1' then    -- rising clock
    if RESET = '1' then
      Q <= "0000";                  -- synchronous Reset (Setup/Hold Time!!)
    else
      Q <= Q + "0001";              -- count ("sequential state", Next-State-Logic)
    end if;
   end if;
end process;