courses:system_design:synthesis:master-slave_flip-flop:rs-ff

RS flip-flop

RS-Flipflop Circuit

S R C Q(t+1) state
0 0 Q(t) hold
0 1 0 reset
1 0 1 set
1 1 - undefined

⎍ = while clock is HIGH

  • 2 statically clocked RS-Latches (clocked, state-driven)
  • complementary controlled by clock C
  1. C=1:
    • Master free : R/S is loaded in master (while clock = 1)
    • Slave blocked : stores previous master value
  2. C=0:
    • Master blocked : stores last R/S-state of HIGH-phase
    • Slave free : enables value of master (1.) to the output
  1. ⎍ positive periode of clock cycle: store data
  2. ↓ falling edge of clock: transmit data
  1. positive period: hold data
  2. negative edge: transfer data

RS Flipflop Timing Behavior

RS high, Clock high, Slave holds

assumption: ideal gate switching time

Notes

assuming R=S=1

C=1

Slave holds the old values of Q and Qn (which we don't know, and which are not equal)

RS high, Clock low, Slave transfers, first level of gates updates its values

Notes

Clock toggles

Slave is “open” and transfers data to the outputs

first internal Master NAND output gets “1”

first internal Slave NAND output gets “0”

RS high, Clock low, Slave transfers, second level of gates updates its values

Notes

Master: Q==Qn=1

Slave: Q==Qn=1

UNDEFINED!!!

Let's look at the internal Q/Qn

The “0” is transferred to the input of the NANDs (this happens simultaneously to the previous discussed transfer of data to the outputs)

RS high, Clock low, Slave transfers, slave gates update their values

td later: Q nodes/outputs change values

Notes

Again: data is transfered to the outputs

  • Master: Q==Qn=0
  • Slave: Q==Qn=0
  • UNDEFINED!!!

td later: and again etc.

  • Master: Q==Qn=1
  • Slave: Q==Qn=1
  • UNDEFINED!!!

oszillates generally with delay of feedbacks

td runtime/delay of feedbacks

oszillates generally with td (behavior depends on the other timing parameters too)

  • R=S=1 is undefined and is to avoid
  • Design of Cross-coupled NAND is difficult, Racing-Conditions - runtimes!
  • is not used in CMOS ASIC Design

RS-FF Circuit

Q(t+1)=[R’ and (S or (S’ and Q))](t)

S R C Q(t+1) state
0 0 Q(t) hold
0 1 0 reset
1 0 1 set
1 1 - avoid

↑ = rising edge of clock

triggering function is "good natured": R=S=1 results D=0 (Reset has priority)

Notes

instead of “avoiding” R=S=1 we do a “reset” - it's nicer :-)


Chapters of System Design > Synthesis > Master-Slave Flip-Flop