courses:system_design:synthesis:master-slave_flip-flop:jk-ff

JK-FF

JK-FF Circuit

  • Q(t+1)=[(Q' and J) or (Q and K')](t)
J K C Q(t+1) state
0 0 Q(t) hold
0 1 0 reset
1 0 1 set
1 1 Q(t)' invert

↑ = rising edge of clock

  • J=K=1 may be used for: inverting (frequency divider, counter)

JK-FF Block

JK-FF Timing Behavior

  • undefined up to first RESET
  • “Toggle”-behavior for J=K=1

Chapters of System Design > Synthesis > Master-Slave Flip-Flop