Table of Contents

 
Preface xvii

VHDL TUTORIAL
1 VHDL : Overview and Application Field 3
1.1 Application Field of HDLs 3
1.1.1 Application of HDLs (1) 4
1.1.2 Application of HDLs (2) 5
1.2 Range of Use 6
1.3 VHDL : Overview 7
1.3.1 VHDL : History 8
1.3.2 VHDL : Application Field 9
1.3.3 ASIC Development 10
1.4 Concepts of VHDL 11
1.4.1 Abstraction 12
1.4.2 Abstraction Levels in IC Design 13
1.4.3 Abstraction Levels and VHDL 14
1.4.4 Description of Abstraction Levels 15
1.4.5 Behavioural Description in VHDL 16
1.4.6 RT Level in VHDL 17
1.4.7 Gate Level in VHDL 18
1.4.8 Information Content of Abstraction Levels 19
1.4.9 Modularity and Hierarchy 20
1.5 Summary 21
2 VHDL Language and Syntax 22
2.1 General 22
2.1.1 Identifier 23
2.1.2 Naming Convention 24
2.2 VHDL Structural Elements 25
2.2.1 Declaration of VHDL Objects 26
2.2.2 Entity 27
2.2.3 Architecture 28
2.2.4 Architecture Structure 29
2.2.5 Entity Port Modes 30
2.2.6 Hierarchical Model Layout 31
2.2.7 Component Declaration 32
2.2.8 Component Instantiation 33
2.2.9 Component Instantiation: Named Signal Association 34
2.2.10 Configuration 35
2.2.11 Configuration: Task and Application 36
2.2.12 Configuration: Example (1) 37
2.2.13 Configuration: Example (2) 38
2.2.14 Process 39
2.2.15 VHDL Communication Model 40
2.2.16 Signals 41
2.2.17 Package 42
2.2.18 Library 43
2.2.19 Design Structure: Example 44
2.2.20 Sequence of Compilation 45
2.2.21 Outlook: Testbench 46
2.2.22 Simple Testbench Example 47
2.2.23 Summary 48
2.3 Sequential Statements 50
2.3.1 IF Statement 50
2.3.2 IF Statement: Example 51
2.3.3 CASE Statement 52
2.3.4 CASE Statement: Example 52
2.3.5 Defining Ranges 53
2.3.6 FOR Loops 54
2.3.7 Loop Syntax 54
2.3.8 Loop Examples 55
2.3.9 WAIT Statement 56
2.3.10 WAIT Statement: Examples 56
2.3.11 WAIT Statements and Behavioural Modelling 57
2.3.12 Variables 58
2.3.13 Variables vs. Signals 58
2.3.14 Use of Variables 59
2.3.15 Variables: Example 60
2.3.16 Global Variables (VHDL'93) 60
2.4 Concurrent Statements 62
2.4.1 Conditional Signal Assignment 62
2.4.2 Conditional Signal Assignment: Example 63
2.4.3 Selected Signal Assignment 64
2.4.4 Selected Signal Assignment: Example 64
2.4.5 Concurrent Statements: Summary 65
2.5 Data Types 66
2.5.1 Standard Data Types 66
2.5.2 Data type `time' 67
2.5.3 Definition of Arrays 68
2.5.4 `integer' and `bit' Types 68
2.5.5 Assignments with Array Types 69
2.5.6 Bit String Literals 70
2.5.7 Concatenation 71
2.5.8 Aggregates 72
2.5.9 Slices of Arrays 73
2.6 Extended Data Types 74
2.6.1 Type Classification 75
2.6.2 Enumeration Types 76
2.6.3 Enumeration Types : Example 77
2.6.4 BIT Type Issues 78
2.6.5 Multivalued Types 78
2.6.6 IEEE Standard Logic Type 79
2.6.7 Resolved and Unresolved Types 80
2.6.8 Std_Logic_1164 Package 80
2.6.9 Resolution Function 81
2.6.10 STD_LOGIC vs. STD_ULOGIC 82
2.6.11 The NUMERIC_STD Package 83
2.6.12 Arrays 84
2.6.13 Multidimensional Arrays 84
2.6.14 Aggregates and Multidimensional Arrays 85
2.6.15 Records 86
2.6.16 Type Conversion 87
2.6.17 Subtypes 88
2.6.18 Aliases 88
2.7 Operators 90
2.7.1 Logical Operators 90
2.7.2 Logical Operations with Arrays 91
2.7.3 Shift Operators: Examples 91
2.7.4 Relational Operators 92
2.7.5 Comparison Operations with Arrays 92
2.7.6 Arithmetic Operators 93
2.8 Subprograms 94
2.8.1 Parameters and Modes 95
2.8.2 Functions 96
2.8.3 Procedures 97
2.9 Subprogram Declaration and Overloading 99
2.9.1 Overloading Example 100
2.9.2 Overloading : Illegal Redeclarations 100
2.9.3 Overloading : Ambiguity 101
2.9.4 Operator Overloading 102
2.9.5 Operator Overloading : Example 102
3 Synthesis 104
3.1 What is Synthesis? 104
3.1.1 Synthesizability 104
3.1.2 Different Language Support for Synthesis 105
3.1.3 How to Do? 106
3.1.4 Essential Information for Synthesis 106
3.1.5 Synthesis Process in Practice 107
3.1.6 Problems with Synthesis Tools 108
3.1.7 Synthesis Strategy 109
3.2 RTL Style 110
3.2.1 Combinational Process: Sensitivity List 111
3.2.2 WAIT Statement <-> Sensitivity List 112
3.2.3 Combinational Process: Incomplete Assignments 113
3.2.4 Clocked Process: Clock Edge Detection 114
3.2.5 Register Inference 115
3.2.6 Asynchronous Set/Reset 116
3.2.7 Summary: Combinational Process (Rules) 117
3.2.8 Summary: Clocked Process (Rules) 117
3.3 Combinational Logic 118
3.3.1 Feedback Loops 118
3.3.2 Coding Style Influence 118
3.3.3 Source Code Optimization 119
3.3.4 Example of a Multiplier 120
3.3.5 Synthesis of Operators 124
3.3.6 IF Structure <-> CASE Structure 125
3.3.7 Implementation of a Data Bus 126
3.4 Sequential Logic 128
3.4.1 Initialization 128
3.4.2 RTL: Combinational Logic and Registers 128
3.4.3 Variables in Clocked Processes 129
3.5 Finite State Machines and VHDL 130
3.5.1 One `State' Process 131
3.5.2 Two `State' Processes 132
3.5.3 How Many Processes? 133
3.5.4 State Encoding 134
3.5.5 Extension of CASE Statement 135
3.5.6 Extension of Type Declaration 136
3.5.7 Hand Coding 137
3.5.8 FSM: Medvedev 138
3.5.9 Medvedev Example 138
3.5.10 'Waveform Medvedev Example 139
3.5.11 FSM: Moore 140
3.5.12 Moore Example 140
3.5.13 Waveform Moore Example 141
3.5.14 FSM: Mealy 142
3.5.15 Mealy Example 142
3.5.16 Waveform Mealy Example 143
3.5.17 Modelling Aspects 144
3.5.18 Registered Output 145
3.5.19 Registered Output Example (1) 146
3.5.20 Waveform Registered Output Example (1) 146
3.5.21 Registered Output Example (2) 147
3.5.22 Waveform Registered Output Example (2) 148
3.6 Advanced Synthesis 149
3.6.1 Parameterization via Constants 150
3.6.2 Parameterization via Generics (1) 150
3.6.3 Parameterization via Generics (2) 151
3.6.4 GENERATE Statement 152
3.6.5 Conditional GENERATE Statement 152
3.6.6 `Parameterization' via Signals 153
4 Simulation 154
4.1 Testbenches 154
4.1.1 Structure of a VHDL Testbench 155
4.1.2 Example 156
4.2 Sequence of Compilation 159
4.3 File I/O 161
4.3.1 Example for File I/O (1/4) 162
4.3.2 File Declaration: VHDL'87 versus VHDL'93 166
4.4 Simulation Flow 167
4.4.1 Elaboration  167
4.4.2 Initialization  168
4.4.3 Execution  168
4.5 Process Execution 170
4.5.1 Concurrent vs. Sequential Execution 170
4.5.2 Signal Update 171
4.5.3 Delta Cycles (1) 172
4.5.4 Delta Cycles (2) 172
4.5.5 Delta Cycles: Example 173
4.5.6 Process Behaviour 174
4.5.7 Postponed Processes 174
4.6 Delay Models 176
4.6.1 Projected Output Waveforms (LRM) 177
4.6.2 Transport Delay (1) 178
4.6.3 Transport Delay (2) 179
4.6.4 Inertial Delay (1) 180
4.6.5 Inertial Delay (2) 181
4.6.6 Inertial Delay (3) 182
5 Project Management 184
5.1 File Organization 184
5.2 Design Components 184
5.2.1 Libraries 185
5.2.2 The LIBRARY Statement 186
5.2.3 The USE Statement 186
5.3 Name Spaces 187
5.3.1 Packages 188
5.3.2 Package Syntax 188
5.3.3 Package Example 189
5.4 Design Reuse 190
5.4.1 Why Reuse? 190
5.4.2 Design for Reuse 191
5.4.3 Bad Example 192
5.4.4 Good Example (1/2) 192
5.4.5 Good Example (2/2) 193

VHDL-AMS TUTORIAL
6 VHDL-AMS 197
6.1 Overview and Introduction 197
6.1.1 Current Design Flow 198
6.1.2 IC Design with VHDL-AMS 199
6.1.3 Application Fields in System Design 200
6.1.4 Discrete System-Continuous System (1) 201
6.1.5 Discrete System-Continuous System (2) 201
6.1.6 Discrete System-Continuous System (3) 202
6.1.7 Simulation Cycle (1) 203
6.1.8 Simulation Cycle (2) 204
6.1.9 Analogue-Digital Coupling 205
6.2 New VHDL-AMS Language Elements 206
6.2.1 Natures 207
6.2.2 Types of Natures 208
6.2.3 Terminals 209
6.2.4 Quantities 210
6.2.5 Branch Quantity 211
6.2.6 Interface Quantity 212
6.2.7 Tolerance 213
6.2.8 Frequency and Noise 214
6.2.9 Analogue-Digital Interface 215
6.2.10 Attributes for Natures and Terminals 216
6.2.11 Attributes for Terminals 217
6.2.12 Attributes for Quantities 218
6.2.13 Attributes for Signals 219
6.2.14 Example: Simple Diode Model 220
6.2.15 Concurrent Break Statement 221
6.2.16 Sequential Break Statement 222
6.2.17 Simultaneous Statements 223
6.2.18 Simultaneous Procedural Statement 224
6.2.19 Simultaneous If/Case Statement 225
6.3 Modelling 226
6.3.1 Analogue Modelling Modes 226
6.3.2 Networks 227
6.3.3 VHDL-AMS vs. SPICE 228
6.3.4 DAEs 229
6.3.5 Signal Flows 230

VHDL WORKSHOP
1 Introduction 233
1.1 Structure of the Exercises 233
1.2 Style Guide 233
1.3 Design Structure 233
2 VHDL Working Environment 235
2.1 Directory Structure 235
2.2 Working Environment 235
2.3 VHDL Code 236
2.4 VHDL Compiler 237
2.5 VHDL Simulator 237
2.6 VHDL Synthesis 239
3 Exercises 241
3.1 STEP 1: A Multiplexer 241
3.2 STEP 2: Extending the Multiplexer 243
3.3 STEP 3: A 7-Segment Display Driver 245
3.4 STEP 4: A Three Digit 7-Segment Display Driver 248
3.5 STEP 5: A Decoder 249
3.6 STEP 6: A Register 252
3.7 STEP 9: A State Machine for the Display 254
3.8 STEP 7: A Timer 256
3.9 STEP 8: A BCD Counter 258
3.10 STEP 9: A State Machine for the Main Controller 262
3.11 STEP 10: The Camera 264

REFERENCE
1 Design Entities and Configurations 269
1.1 Entity  269
1.2 Architecture  270
1.3 Configuration  272
2 Subprograms and Packages 274
2.1 Subprogram Declaration  274
2.2 Subprogram Body  275
2.3 Overloading 277
2.4 Resolution Function  279
2.5 Package Declaration  280
2.6 Package Body  281
2.7 Conformance Rules  283
3 Types 284
3.1 Scalar Types  284
3.2 Compound Types  285
3.3 Access Types  286
3.4 File Types  287
4 Declarations 288
4.1 Type Declarations  288
4.2 Subtype Declarations  289
4.3 Constant Declarations  291
4.4 Signal Declarations  292
4.5 Variable Declarations  294
4.6 File Declarations  296
4.7 Interface Declarations  298
4.8 Alias Declarations  298
4.9 Attribute Declarations  301
4.10 Component Declarations  302
4.11 Group Template Declarations  303
4.12 Group Declaration  304
5 Specification 306
5.1 Attribute Specification  306
5.2 Configuration Specification  307
5.3 Disconnection Specification  309
6 Names 311
6.1 Name  311
6.2 Simple Names  311
6.3 Selected Names  311
6.4 Indexed Names  312
6.5 Range Names  312
6.6 Attribute Names  313
7 Expressions 314
7.1 Expression  314
7.2 Logic Operators  314
7.3 Relational Operators  315
7.4 Shift Operators  316
7.5 Adding Operators  317
7.6 Multiplying Operators  318
7.7 Miscellaneous Operators 319
7.8 Literals  320
7.9 Aggregates  320
7.10 Function Call  321
7.11 Qualified Expression  321
7.12 Type Conversion 322
7.13 Allocator  322
7.14 Static Expression  323
7.15 Universal Expression  324
8 Sequential Statements 325
8.1 Wait  325
8.2 Assertion  326
8.3 Report  328
8.4 Signal Assignment  329
8.5 Variable Assignment  331
8.6 Procedure Call  332
8.7 IF  333
8.8 CASE  335
8.9 LOOP  336
8.10 NEXT  338
8.11 EXIT  339
8.12 RETURN  341
8.13 NULL  342
9 Concurrent statements  343
9.1 Block  343
9.2 Process  344
9.3 Concurrent Procedure Call  346
9.4 Concurrent Assertion  348
9.5 Concurrent Signal Assignment  349
9.6 Component Instantiation  352
9.7 Generate Statement  355
10 Miscellaneous 358
10.1 Visibility and Validity Ranges 358
10.2 Use Statements  361
10.3 Design Units and Their Analysis 362
11 Elaboration and Simulation 363
11.1 Elaboration of a Blockheader 363
11.2 Elaboration of a Declaration 365
11.3 Elaboration of a Statement Part 370
11.4 Dynamic Elaboration 373
11.5 Elaboration of a Design Hierarchy 374
11.6 Execution of a Model 375
12 Lexical Elements 379
12.1 Character Set  379
12.2 Delimiters  379
12.3 Identifiers  380
12.4 Abstract Literals  380
12.5 Character Literals  381
12.6 String Literals  381
12.7 Bit String Literals  382
12.8 Comments  382
12.9 Reserved Words  383
12.10 Replacing Characters  383
13 Predefined Attributes 384
14 Package STANDARD 393
15 Package TEXTIO 395
16 BNF 397

LITERATURE

 413

INDEX

 415