------------------------------- --Example VHDL Code-- ------------------------------- SIGNAL mySignal : bit; -- an example signal MYsignal <= '0', -- start with '0', '1' AFTER 10 ns, -- and toggle after '0' AFTER 10 ns, -- every 10 ns '1' AFTER 10 ns;
VHDL is generally case insensitive which means that lower case and upper case letters are not distinguished. This can be exploited to define own rules for formatting the VHDL source code. VHDL keyword could for example be written in lower case letters and self defined identifiers in upper case letters. This convention is valid for the following slides.
Comments can be inserted after two consecutive hyphens. From this point forward to the end of the current line everything will be considered as comment.
Statements are terminated in VHDL with a semicolon. That means as many line breaks or other constructs as wanted can be inserted or left out. Only the semicolons are considered by the VHDL compiler.
List are normally separated by commas. Signal assignments are notated with the composite assignment operator ’⇐’.
Self defined identifier as defined by the VHDL 87 standard may contain letters, numbers and underscores and must begin with a letter. Further no VHDL keywords may be used. The VHDL 93 standard allows to define identifiers more flexible as the next slide will show.
mySignal_23 -- normal identifier rdy, RDY, Rdy -- identical identifiers vector_&_vector -- X: special character last of Zout -- X: white spaces idle__state -- X: consecutive underscores 24th_signal -- X: begins with a numeral open, register -- X: VHDL keywords
\mySignal_23\ -- extended identifier \rdy\, \RDY\, \Rdy\ -- different identifiers \vector_&_vector\ -- legal \last of Zout\ -- legal \idle__state\ -- legal \24th_signal\ -- legal \open\, \register\ -- legal
Simple identifiers as defined by the VHDL 87 standard may contain letters, numbers and underscores. So ’mySignal_23’ is a valid simple identifier. Further VHDL is case insensitive that means ’rdy’, ’RDY’ and ’Rdy’ are identical. In particular the identifier has to begin with a letter, so ’24th_signal’ is not a valid identifier. Also not allowed are graphical characters, white spaces, consecutive underscores and VHDL keywords.
In the VHDL 93 standard a new type of identifiers is defined. They are called extended identifiers and are enclosed in back slashes. Within these back slashes nearly every combination of characters, numbers, white spaces and underscores is allowed. The only thing to consider is that extended identifiers are now case sensitive. So ’/rdy/’, ’/RDY/’ and ’/Rdy/’ are now three different identifiers.
architecture CONVENTION of NOTATION is end architecture CONVENTION;
The naming convention for this book are that VHDL keyword are written in lower case letters while user defined identifiers are written in upper case letters. If something has to be highlighted it is done by writing it in bold letters.
There are several selfexplaining icons. They mark special issues about the VHDL’93 syntax (compared to that of VHDL’87), things to remark, synthesis aspects and special tips.