Table of Contents

Sequential Logic

Sequential logic is the general term for designs containing storing elements, especially flip flops.

Initialization

process
begin
   wait until CLK’event and CLK=’1’: -- without reset not recommended
   DATA <= INPUT;
end process;

Register without Reset 

process (CLK,RESET)
begin
   if (RESET = ‘1’) then
       DATA <= ‘0’;
   elsif (CLK’event and CLK=’1’) then -- correct
       DATA <= INPUT;
   end if;
end process;

Register with Reset

Notes

While all signals can be initialized prior to simulation by specifying default values, an explicit reset mechanism is necessary to guarantee that the designs behaves the same way whenever it is powered up.

Usually, a dedicated reset signal is used for this purpose.

Please note that asynchronous behavior can be modelled with processes with sensitivity list, only, i.e. the process has to react upon the clock and the reset signal.

RTL - Combinational Logic and Registers

Combinational Logic and Registers 

LOGIC_A: process
begin
 
wait until CLK’event and CLK=’1’;
    --logic A
end process LOGIC_A;
 
LOGIC_B: process (ST)
begin
   --logic B
end process LOGIC_B;
LOGIC_AB: process
begin
 
wait until CLK’event and CLK=’1’;
    -- logic A and logic B
end process LOGIC_AB;

Notes

Additionally, all signals that may receive new values within a clocked process infer flip flops.

Though it is recommended from a theoretic point of view that registers and combinational logic are modelled with separate processes, it is often convenient to place the calculation of new flip flop values in the same process.

Output-Logic: Postprocessing of register values, however, has to be performed within another process or with concurrent statements.

Variables in Clocked Processes

VAR_1:process(CLK)
   variable TEMP : integer;
begin
 
  if (CLK’event and CLK =’1’) then
      TEMP := INPUT *2;
      OUTPUT_A <= TEMP +1 ;  -- Reg 32
      OUTPUT_B <= TEMP +2 ;  -- Reg 32
  end if;
end process VAR_1;
VAR_2:process(CLK)
   variable TEMP : integer;
begin
 
  if (CLK’event and CLK =’1’) then
      OUTPUT <= TEMP + 1 ;   -- Reg 32
      TEMP   := INPUT * 2 ;  -- Reg 32
  end if;
end process VAR_2;

Notes

The hardware implementation of variables depends on their use in the process.

The VHDL language guarantees that variables still hold their old values when a process is executed again.

If this value is not used, however, because it is always updated prior to its use, a storing element will become redundant.

Consequently, flip flops are inferred for variables in clocked processes only if they are read before they will be updated.

In the VAR_1 process, the variable is always set to INPUT*2 whenever an active clock edge is detected. Thus, TEMP is treated as shortcut for the expression and is not visible in the final netlist.

In VAR_2, however, the value of TEMP is used to calculate the new value of the OUTPUT signal, i.e. a register bank (integer: at least 32 bit) will be generated.

Quiz

Synthesis:
Combinational Logic:
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