T=J=K
T | C | Q(t+1) | state |
---|---|---|---|
1 | ↑ | Q'(t) | invert |
0 | ↑ | Q(t) | hold |
↑ = rising edge of clock
simple structure - but problems by application because of real runtimes!!!!
JK-FF with Reset:
U_D_MS: D_MS port map (CLK, D, Q, Qn); D <= '0' when RESET = '1' else (Qn and J) or (Q and not K);