important for the ASIC Synthesis:
D stable while
that is all nodes in master part become stable values/levels
Output-Delay-Time: TOD delay at gate output
Problem: gates are faster (in relation to wires)
TOD ↓ but Tskew ↑
Static-Timing-Analysis: checking after layout if the sum of all output-delays and real wire-delay-times results in setup/hold-time violations
port ( RESET : in std_ulogic; CLK : in std_ulogic; Q : buffer std_logic_vector (3 downto 0) );
process (CLK) begin if CLK'event and CLK='1' then -- rising clock if RESET = '1' then Q <= "0000"; -- synchronous Reset (Setup/Hold Time!!) else Q <= Q + "0001"; -- count ("sequential state", Next-State-Logic) end if; end if; end process;