S | R | C | Q(t+1) | state |
---|---|---|---|---|
0 | 0 | ⎍ | Q(t) | hold |
0 | 1 | ⎍ | 0 | reset |
1 | 0 | ⎍ | 1 | set |
1 | 1 | ⎍ | - | undefined |
⎍ = while clock is HIGH
assumption: ideal gate switching time
assuming R=S=1
C=1
Slave holds the old values of Q and Qn (which we don't know, and which are not equal)
Clock toggles
Slave is “open” and transfers data to the outputs
first internal Master NAND output gets “1”
first internal Slave NAND output gets “0”
Master: Q==Qn=1
Slave: Q==Qn=1
UNDEFINED!!!
Let's look at the internal Q/Qn
The “0” is transferred to the input of the NANDs (this happens simultaneously to the previous discussed transfer of data to the outputs)
td later: Q nodes/outputs change values
Again: data is transfered to the outputs
td later: and again etc.
td runtime/delay of feedbacks
oszillates generally with td (behavior depends on the other timing parameters too)
Q(t+1)=[R’ and (S or (S’ and Q))](t)
S | R | C | Q(t+1) | state |
---|---|---|---|---|
0 | 0 | ↑ | Q(t) | hold |
0 | 1 | ↑ | 0 | reset |
1 | 0 | ↑ | 1 | set |
1 | 1 | ↑ | - | avoid |
↑ = rising edge of clock
instead of “avoiding” R=S=1 we do a “reset” - it's nicer