D-FF
- Overview
- D-FF in VHDL

D-FF

Overview

D-FF Circuit

D	C	Q(t+1)
1	↑	1
0	↑	0

↑ = rising edge of clock

transmission-gates = simple switch:

Transmission Gate

2 complementary D-Latches are state controlled by clock

D-FF Block

C=0: master is transparent, following the input level, slave is locked (holds)
C=1: Master is blocking, feeds immediately to the pos. edge of clock and the value seen on D is on the output immediately, Slave is transparent

Positive edge: Q = D standard FF in CMOS-ASIC design!!

D-FF Simulation Flow

D-FF in VHDL

D_FF: process (CLK)
begin
  if CLK'event and CLK='1' then
    Q <= D;
  end if;
end process;

D_LATCH: process (CLK, D)
begin
  if CLK='1' then
    Q <= D;
  end if;
end process;

Notes

Here, a D-flip-flop controlled by a clock pulse edge is described. If an event occurs at the clock signal and this event has the value ONE, the value of the pin D will be transferred to the pin Q. (You could also await the negative clock pulse edge, then must be: CLK='0').

Table of Contents

D-FF

Overview

D-FF in VHDL

Notes