Example of a Multiplier

• 2 x 2 bit multiplier
  • Inputs: A1, A0, B1, B0 : 2 bit
  • Outputs: C3, C2, C1, C0 : 4 bit

entity MULTIPLIER is 
 port (A0  : in  bit;
       A1  : in  bit;
       B0  : in  bit;
       B1  : in  bit;
       C0  : out bit;
       C1  : out bit;
       C2  : out bit;
       C3  : out bit);
end MULTIPLIER;

• 3 different VHDL implementations
  • Function table
  • Synthesis “by hand” (boolean functions for the outputs)
  • Use of VHDL integer types and operators

architecture RTL_TABLE of MULTIPLIER is 
  signal A_B : bit_vector ( 3 downto 0);
begin
  A_B <= A1 & A0 & B1 & B0;
  MULTIPLY : process (A_B)
  begin
   case A_B is 
    when “0000” => (C3,C2,C1,C0) <= “0000”;
    when “0001” => (C3,C2,C1,C0) <= “0000”;
    when “0010” => (C3,C2,C1,C0) <= “0000”;
    when “0011” => (C3,C2,C1,C0) <= “0000”;
    when “0100” => (C3,C2,C1,C0) <= “0000”;
    when “0101” => (C3,C2,C1,C0) <= “0001”;
    when “0110” => (C3,C2,C1,C0) <= “0010”;
    when “0111” => (C3,C2,C1,C0) <= “0011”;
   ...
    when “1100” => (C3,C2,C1,C0) <= “0000”;
    when “1101” => (C3,C2,C1,C0) <= “0011”;
    when “1110” => (C3,C2,C1,C0) <= “0110”;
    when “1111” => (C3,C2,C1,C0) <= “1001”;
  end case;
 end process MULTIPLY;
end RTL_TABLE;

• An internal signal is used that combines all input signals
• The internal signal is generated concurrently, i.e. it is updated whenever the input changes
• The function table is realized as case statement and thus has to placed within a process. The internal signal is the only signal that controls the behavior.

architecture RTL_MINTERM of MULTIPLIER is
begin
 
  C0 <= A0 and B0;
 
  C1 <= (A0 and not A1 and B1) or 
        (A0 and not B0 and B1) or
        (not A0 and A1 and B0) or
        (A0 and B0 and not B1);
 
  C2 <= (A1 and B1 and not B0) or 
        (A1 and not A0 and B1);
 
  C3 <= A1 and A0 and B1 and B0;
 
end  RTL_MINTERM;

• The minterm functions are realized directly as concurrent statements

library IEEE;
use IEEE.NUMERIC_BIT.all;
 
architecture RTL_INTEGER
of MULTIPLIER is 
  signal A_VEC : unsigned (1 downto 0 );
  signal B_VEC : unsigned (1 downto 0 );  
  signal A_INT : integer range 0 to 3;
  signal B_INT : integer range 0 to 3;
  signal C_VEC : unsigned (3 downto 0 );
  signal C_INT : integer range 0 to 9;
begin
 
  A_VEC <= A1 & A0;
  A_INT <= TO_INTEGER(A_VEC);
  B_VEC <= B1 & B0;
  B_INT <= TO_INTEGER(B_VEC);
 
  C_INT <= A_INT * B_INT;
 
  C_VEC <= TO_UNSIGNED(C_INT, 4);
 
  (C3, C2, C1, C0) <= C_VEC;
end RTL_INTEGER;

• The NUMERIC_BIT package provides all necessary functions to convert bit vector to integer values and vice versa
• Internal signals are used to generate bit vectors and integer representations of the port signals. The bit vectors shall be treated as unsigned binary values.
• The signal bit input signals are concatenated to vectors and converted to integer data types
• the multiplication s realized via the standard VHDL operator
• The size of the target vector must be specified when converting integers back to bit vectors
• Finally, the bit vector elements are assigned to the output ports