====== LAB 1: A Multiplexer ======
===== Synopsis =====
Your first task is to write the VHDL description of a multiplexer. The camera display shall either show the number of pictures that have already been taken or the current exposure time. The following figure shows a schematic of the multiplexer:

{{:vhdl_workshop:workshop_multiplexer.svg?nolink&500|The Multiplexer}}

==== Behaviour ====
The multiplexer output shall be equal to its EXP_TIME input when the control signal SHOW_TIME is ’1’. Else, DISP_PHOTO shall be set to NO_PICS.

==== Data types ====
As EXP_TIME and NO_PICS hold whole-numbered values, **integer** is the natural data type for the data signals. **Bit** might be the natural choice for the SHOW_TIME control signal as it holds only two reasonable values. However, you should use **std_ulogic** instead, as multi-valued logic is especially suited to model actual hardware.

==== To do ====
  * Create a VHDL model of the multiplexer.
  * Use your VHDL compiler to find and eliminate all syntax errors.
  * Create a testbench to verify the proper behaviour.
  * Compile the testbench.
  * Run the simulation. Trace the signal values in a waveform display for verification.
  * Synthesize the model using your favourite synthesis tool.

===== Implementation =====
<code vhdl DISP_MUX.VHD>
library ieee;
use ieee.std_logic_1164.all;

entity DISP_MUX is
  port(EXP_TIME   : in integer;
       NO_PICS    : in integer;
       SHOW_TIME  : in std_ulogic;
       DISP_PHOTO : out integer;);
end DISP_MUX;

architecture RTL of DISP_MUX is
begin
  process(NO_PICS, EXP_TIME)
  begin
    if SHOW_TIME = '1' then
      -- output = exposure time
    else
      -- output = picture count
    end if;
  end process;
end RTL;
</code>

===== Testbench =====
<code vhdl TB_DISP_MUX.VHD>
library ieee;
use ieee.std_logic_1164.all;

entity TB_DISP_MUX is
end TB_DISP_MUX;

architecture TEST of TB_DISP_MUX is
  component DISP_MUX
    port(EXP_TIME   : in integer;
         NO_PICS    : in integer;
         SHOW_TIME  : in std_ulogic;
         DISP_PHOTO : out integer);
  end component;

  signal W_EXP_TIME   : integer := 0;
  signal W_NO_PICS    : integer := 0;
  signal W_SHOW_TIME  : std_ulogic := '0';
  signal W_DISP_PHOTO : integer;

begin
  DUT : DISP_MUX
    port map (
      EXP_TIME   => W_EXP_TIME,
      NO_PICS    => W_NO_PICS,
      SHOW_TIME  => W_SHOW_TIME,
      DISP_PHOTO => W_DISP_PHOTO);
  
  STIMULI : process
  begin
    -- DISP_PHOTO = 0
    wait for 30 ns;
    
    W_NO_PICS <= 2;
    W_EXP_TIME <= 64;
    -- DISP_PHOTO = 2
    wait for 20 ns;
    
    W_NO_PICS <= 10;
    -- DISP_PHOTO = 10
    wait for 20 ns;
    
    W_SHOW_TIME <= '1';
    -- DISP_PHOTO = 64
    wait for 20 ns;
    
    W_NO_PICS <= 20;
    -- no changes
    wait for 20 ns;
    
    W_SHOW_TIME <= '0';
    -- DISP_PHOTO = 20
    wait for 20 ns;
    
    wait;
  end process;
end TEST;

configuration CFG_TB_DISP_MUX of TB_DISP_MUX is
  for TEST
  end for;
end CFG_TB_DISP_MUX;
</code>

===== Results =====
The waveform display shows that DISP_PHOTO always holds the current value of the selected input port. Changes to this value are transferred to the output immediately whereas modifications to the other port do not affect the output. Thus, the multiplexer behaves as specified. When inspecting the synthesized result, please note that the bus width for the data signals is 32 bit. This is because their data type was specified as integer without any range restrictions. Generally, omitting the range specification will result in a waste of resources. This is one of the reasons for a redesign of the multiplexer as next step.