====== Use-statements ======
===== use_clause =====
<code vhdl>use selected_name { , selected_name } ;</code>

===== Parents =====
  * entity_declarative_part
  * architecture_declarative_part
  * configuration_declarative_part
  * package
  * package_body
  * block_declarative_part
  * function_declarative_item
  * procedure_declarative_item
  * process_declarative_item

===== Comment =====
The **USE** -statement can also be placed as a context-statement in front of every library module such as entity, architecture, package, package body and configuration.

===== Examples =====
All packages from the default-library //work// are integrated.
<code vhdl>
USE work. ALL ;
</code>

----

All elements of the package //my_package// from the library //work// are integrated.
<code vhdl>USE work.my_package. ALL ;</code>

----

The function //my_function// from the package //my_package// in the library //work// is integrated.
<code vhdl>USE work.my_package.my_function ;</code>

----

All elements from the packages //pkg_1// and //pkg_3// are integrated; from package //pkg_2// only the procedure //proc_1// is integrated.
<code vhdl>
USE
      lib_1.pkg_1. ALL ,
      lib_1.pkg_2.proc_1,
      lib_2.pkg_3. ALL ;
</code>

===== Overloading resolution =====
Overloading is defined for [[.:Overloading|subprograms, operators]] and [[.:Scalar types|values of enumeration types]].

Overloading is the simultaneous [[.:Visibility and validity ranges|visibility]] of several subprograms, operators or of object values which have the same name and may belong to different enumeration types. By using overloading it is possible to extend a function's range of application. The several variants of a subprogram or an operator only differ in the type and number of their arguments and results. VHDL-programs recognise from the context (i.e. from the number and types of arguments) which of the visible variants is to be used. If a definite decision is not possible, i.e. if several visible alternative prove to be ``suitable`` for the required task an error is reported.

With the concept of overloading, VHDL-models become easier to survey as it is not necessary to name a new designator for every variant of a certain functionality.