====== Process ======
===== process_statement =====
<code vhdl>
[ process _label : ]
    [ postponed ] process [ ( sensitivity_list ) ] [ is ]
        process_declarative_part
    begin
        process_statement_part
    end [ postponed ] process [ process _label ] ;
</code>

===== Parents =====
  * entity_statement_part
  * architecture_statement_part
  * block_statement_part

===== Further definitions =====
==== label ====
  * [[.:bnf#identifier]]

==== sensitivity_list ====
''signal _[[.:bnf#name]] { , signal _[[.:bnf#name]] }''

==== process_declarative_part ====
''{ [[.:bnf#process_declarative_item]] }''

==== process_statement_part ====
''{ [[.:bnf#sequential_statement]] }''

===== Comments =====
Alternative for a sensitivity list after the keyword **PROCESS** the following WAIT statement can be used at the end of the process: **WAIT ON** sensitivity_list ;

A process may only have a sensitivity list or one respective several WAIT statements.

A **PROCESS** -statement within the statement-part of an **ENTITY** has to be a passive **PROCESS** -statement.

A process with the keyword **POSTPONED** is called "postponed process". This process will always (given there is only one postponed process) be executed in the last delta cycle of a simulation cycle. This implies that only signal assignments with a delay greater than 0 are allowed (Otherwise other processes would be executed in subsequent delta cycles).

===== Examples =====
This process describes a flipflop.

The positive clock-edge is detected by the **WAIT** -statement and by checking the condition //clock = `1`// . 2 ns after the clock-edge the value of input //d// is on output //q// .
<code vhdl>
PROCESS
BEGIN
   IF ( clock = '1' ) THEN
      q <= d AFTER 2 ns ;
   END IF ;
   WAIT ON clock ;
END PROCESS ;
</code>

----

This named process also describes a flipflop.

The positive clock-edge is detected by the sensitivity list and by checking the condition //clock = `1`// . 1 ns after the clock-edge the value of input //d// is on output //q// .
<code vhdl>
reg : PROCESS ( clock )
BEGIN
   IF clock = '1' THEN
      q <= d AFTER 1 ns ;
   END IF ;
END PROCESS reg ;
</code>

----

This is an example of a passive process.

With the positive clock edge only the condition //reset = '1'// is checked and a warning given if necessary.
<code vhdl>
passive : PROCESS
BEGIN
   WAIT ON clock ;
   IF clock = '1' THEN
      ASSERT reset = '1' ;
      REPORT "reset is active!" ;
      SEVERITY warning ;
   END IF ;
END PROCESS passive ;
</code>

----

This process contains two WAIT -statements.

The first **WAIT** -statement interrupts the process until //sig_2 = 0// whereas the second **WAIT** -statement causes a change of one of the two signals //sig_1// or //sig_2// to be waited for.
<code vhdl>
PROCESS
   VARIABLE v1, v2 : integer := 1 ;
BEGIN
   sig_1 <= v1 AFTER 1 ns ;
   WAIT UNTIL sig_2 = 0 ;
   v2 := v2 * 2 ;
   v1 := v2 + 4 ;
   sig_1 <= v1 AFTER 1 ns ;
   WAIT ON sig_1, sig_2 ;
   FOR i IN 1 TO 3 LOOP
      v1 := v1 + v2 ;
   END LOOP ;
END PROCESS ;
</code>

----

A postponed process is defined to assert the value of a signal.
<code vhdl>
POSTPONED PROCESS (testsig)
BEGIN
   ASSERT testsig=expected_value
   REPORT "testsig differs from" &
          "expected value!"
   SEVERITY error ;
END POSTPONED PROCESS ;
</code>