====== Component declarations ======
===== component_declaration =====
<code vhdl>
component identifier [ is ]
    local _generic_clause ]
    [ local _port_clause ]
end component [ component _simple_name ] ;
</code>

===== Parents =====
  * architecture_declarative_part
  * package
  * block_declarative_part

===== Further definitions =====
==== identifier ====
  * [[.:bnf#basic_identifier]]
  * [[.:bnf#extended_identifier]]

==== generic_clause ====
''**generic** ( [[.:bnf#generic_list]] ) ;''

==== port_clause ====
''**port** ( [[.:bnf#port_list]] ) ;''

===== Examples =====
The component //gen_clock// is declared whose only interface to the outside is the output //clk//.
<code vhdl>
COMPONENT gen_clock
   PORT ( clk : OUT tri_bit ) ;
END COMPONENT ;
</code>

----

The component //adder_8_bit// declared here has the inputs //a// , //b// and //cin// and the outputs //sum// and //cout// .
<code vhdl>
COMPONENT adder_8_bit
   PORT (a, b : IN bit_vector(1 TO 8);
         cin : IN bit ;
         sum : OUT bit_vector(1 TO 8);
         cout: OUT bit ) ;
END COMPONENT ;
</code>

----

The component //adder_n_bit// declared here is parameterised via the generic n.

The width of the input vectors //a// and //b// and that of the output vector //sum// is determined by the value of the generic //n// .
<code vhdl>
COMPONENT adder_n_bit
   GENERIC ( n : positive ) ;
   PORT (a, b : IN bit_vector(1 TO n);
         cin : IN bit ;
         sum : OUT bit_vector(1 TO n);
         cout: OUT bit ) ;
END COMPONENT ;
</code>