====== Attribute specification ======
===== attribute_specification =====
<code vhdl>
attribute attribute_designator of entity_specification is expression ;
</code>

===== Parents =====
  * entity_declarative_part
  * architecture_declarative_part
  * configuration_declarative_part
  * package
  * block_declarative_part
  * function_declarative_part
  * procedure_declarative_part
  * process_declarative_part

===== Further definitions =====
==== attribute_designator ====
''attribute _[[.:bnf#simple_name]]''

==== entity_specification ====
''[[.:bnf#entity_name_list]] : [[.:bnf#entity_class]]''

==== expression ====
  * [[.:bnf#relation]] { and relation }
  * relation { or relation }
  * relation { xor relation }
  * relation [ nand relation ]
  * relation [ nor relation ]
  * relation { xnor relation }

===== Examples =====
Values for the attribute //pin_number// are determined. For the signal //cin// the attribute value is //10// and for the signal //cout// it is //5// .
<code vhdl>
ATTRIBUTE pin_number OF cin :
      SIGNAL IS 10 ;

ATTRIBUTE pin_number OF cout :
      SIGNAL IS 5 ;
</code>

----

For the label //adder_1// the value of the attribute //instance_location// is (//10,15//) ; for all other labels it is (//25,65//) .
<code vhdl>
ATTRIBUTE instance_location OF
      adder_1 : LABEL IS ( 10, 15 ) ;

ATTRIBUTE instance_location OF
      OTHERS : LABEL IS ( 25, 65 ) ;
</code>

----

  * The attribute //author// of the entity //add_entity// is seized by the string //Martin// .
  * The attribute //is_generic// of the component //cmos_nand// is seized by the value //false// .
  * The attribute //creation_date// of the architecture //add_arc// is seized by the Record (//14,Aug,95//) .
  * The attribute //safety// of the procedure //arithm_conv// is seized by the value //bug// .
  * The attribute //confidentiality// of the package //cmos_pkg// is seized by the value //restrictive// .
<code vhdl>
ATTRIBUTE author OF add_entity :
      ENTITY IS "Martin" ;
ATTRIBUTE is_generic OF cmos_nand :
      COMPONENT IS false ;
ATTRIBUTE creation_date OF add_arc :
      ARCHITECTURE IS (11, aug, 95) ;
ATTRIBUTE safety OF arithm_conv :
      PROCEDURE IS bug ;
ATTRIBUTE confidentiality OF    cmos_pkg : PACKAGE IS restrictive ;
</code>

----

By using [[.:predefined attributes]] the loop instruction can be written in a different way as well:
<code vhdl>
FOR i IN a1'LOW TO a1'HIGH

FOR i IN a1'RIGHT TO a1'LEFT

FOR i IN a1'REVERSE_RANGE

FOR i IN a1'RANGE
</code>
<code vhdl>
SIGNAL a1: bit_vector(3 DOWNTO 0) ;
...
PROCESS (a)
   BEGIN
   z<= "0000" :
   FOR i in 0 TO 3 LOOP
      IF (a = i) THEN
         z(i) <= '1' ;
      END IF ;
   END LOOP ;
END PROCESS ;
...
</code>