====== History of Verilog, SystemVerilog ======
===== For completeness' sake =====
  * invented 1984 as proprietary **hardware modeling** and **simulation language**
  * purchased by [[https://en.wikipedia.org/wiki/Cadence_Design_Systems|Cadence]] in 1990, transferred into public domain 
  * became IEEE Std. 1364-1995 (aka. **Verilog-95**)
  * extensions of Verilog-95 became [[https://en.wikipedia.org/wiki/Institute_of_Electrical_and_Electronics_Engineers|IEEE]] Standard 1364-2001 (Verilog-2001) - still the dominant flavor of Verilog supported by most [[https://en.wikipedia.org/wiki/Electronic_design_automation|EDA]] tools
  * **Verilog 2005** ([[https://en.wikipedia.org/wiki/Institute_of_Electrical_and_Electronics_Engineers|IEEE]] Std. 1364-2005): minor corrections, few new features
  * **[[https://en.wikipedia.org/wiki/Verilog-AMS|Verilog-AMS]]**: attempts to integrate **a**nalog and **m**ixed **s**ignal modelling with traditional Verilog, separate part of Verilog standard
  * **[[https://en.wikipedia.org/wiki/SystemVerilog|SystemVerilog]]** (IEEE Std. P1800-2005): [[https://en.wikipedia.org/wiki/Superset|superset]] of Verilog-2005 with many new features and capabilities to aid **design-verification** and **-modelling** 
  * **2009: SystemVerilog** and **Verilog** standards merged into **SystemVerilog 2009** (IEEE Standard 1800-2009) - i.e. a combined [[https://en.wikipedia.org/wiki/Hardware_description_language|Hardware Description Language]] and [[https://en.wikipedia.org/wiki/Hardware_verification_language|Hardware Verification Language]] based on extensions to [[https://en.wikipedia.org/wiki/Verilog|Verilog]]

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=== Notes ===
  * Cadence transferred Verilog into the public domain under the Open Verilog International (OVI) (now known as [[https://en.wikipedia.org/wiki/Accellera|Accellera]]) organization. 
  * **SystemVerilog** started with the donation of the **Superlog language** (Co-Design Automation) to [[http://www.accellera.org/|Accellera]] in 2002.[1] The bulk of the verification functionality is based on the **[[https://en.wikipedia.org/wiki/OpenVera|OpenVera]] language** donated by [[https://en.wikipedia.org/wiki/Synopsys|Synopsys]]. 
  * The feature-set of SystemVerilog can be divided into two distinct roles:
    - **SystemVerilog for RTL design** is an **extension of [[https://en.wikipedia.org/wiki/Verilog|Verilog-2005]]**; all features of that language are available in SystemVerilog.
    - SystemVerilog **for verification** uses extensive [[https://en.wikipedia.org/wiki/Object-oriented_programming|object-oriented programming]] techniques and is **more closely related to [[https://en.wikipedia.org/wiki/Java_%28programming_language%29|Java]] than Verilog**.
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