====== VHDL Structural Elements ======
===== VHDL Units =====

^ Entity:        | Interface        |
^ Architecture:  | Implementation, behavior, function |
^ Configuration: | Model chaining, structure, hierarchy |
^ Process:       | Concurrency, event controlled        |
^ Package:       | Modular design, standard solution, data types, constants |
^ Library:       | Compilation, object code        |

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=== Notes ===
The main units in VHDL are entities, architectures, configurations and packages (together with package bodies).

While an entity describes an interface consisting of the port list most of the time, an architecture contains the description of the function of the corresponding module. In general, a configuration is used for simulation purposes, only. In fact, the configuration is the only simulatable object in VHDL as it explicitly selects the entity/architecture pairs to build the complete model. Packages hold the definition of commonly used data types, constants and subprograms. By referencing a package, its content can be accessed and used.

Another important construct is the process. While statements in VHDL are generally concurrent in nature, this construct allows for a sequential execution of the assignments. The process itself, when viewed as a whole object, is concurrent. In reality, the process code is not always executed. Instead, it waits for certain events to occur and is suspended most of the time.

A library in VHDL is the logical name of a collection of compiled VHDL units (object code). This logical name has to be mapped by the corresponding simulation or synthesis tool to a physical path on the file system of the computer.
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===== PCB analogy =====
{{:courses:system_design:vhdl_language_and_syntax:vhdl_structural_elements:folie48_stucturalelements.svg?nolink&700|Structural Elements}}

^ VHDL unit               ^ PCB analogy ^
| Entity                  | Footprint   |
| Component declaration   | Chip socket |
| Component Instantiation | Package     |
| Architecture            | Chip die    |


===== Declaration of VHDL Objects =====
|               ^ Entity ^ Architecture ^ Process/ Subprogram ^ Package ^
^ Subprogram    | x      | x            | x                   | x       |
^ Component     |        | x            |                     | x       |
^ Configuration |        | x            |                     |         |
^ Constant      | x      | x            | x                   | x       |
^ Data Type     | x      | x            | x                   | x       |
^ Port          | x      |              |                     |         |
^ Signal        |        | x            | x<sup>a</sup>       | x       |
^ Variable      |        |              | x<sup>b</sup>       |         |

a. Signals may not be declared in functions

b. Global variables (VHDL’93) may also be declared in entities, architectures and packages

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=== Notes ===
The table lists the legal places for the declaration of different objects:
  * A subprogram is similar to a function in C and can be called many times in a VHDL design. It can be declared in the declarative part of an entity, architecture, process or even another subprogram and in packages. As a subprogam is thought to be used in several places (architectures) it is useful to declare it in a package, always.
  * Components are necessary to include entity/architecture pairs in the architecture of the next higher hierarchy level. These components can only be declared in an architecture or a package. This is useful, if an entity/architecture pair might be used in several architectures as only one declaration is necessary in this case.
  * Configurations, themselves, are complete VHDL design units. But it is possible to declare configuration statements in the declarative part of an architecture. This possibility is only rarely used, however, as it is better to create an independent configuration for the whole model.
  * Constants and data types can be declared within all available objects.
  * Port declarations are allowed in entities, only. They list those architecture signals that are available as interface to other modules. Additional internal signals can be declared in architectures, processes, subprograms and packages. Please note that signals can not be declared in functions, a special type of a subprogram.
  * Generally, variables can only be declared in processes and subprograms. In VHDL’93, global variables are defined which can be declared in entities, architectures and packages.
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