====== Quiz ======

<quizlib id="quizstructuralelements" rightanswers="[['a1','a2'],['a1'],['a0'],['a1','a2'],['a0','a1'],['a0']]" submit="Check answers">
<question title="An architecture..." type="checkbox"> ...can exist on its own| ...can exist only together with its dedicated design entity. | ...contains a description of the module's behavior.</question>
<question title="In VHDL, sequential statements..." type="radio"> ...are defined in the architecture| ...are defined in the process</question>
<question title="The configuration..." type="checkbox"> ...generates the simulateable object.| ...is declared within the architecture. | ...chooses the entity for a certain architecture.</question>
<question title="The component declaration..." type="checkbox"> ...integrates a certain entity into a preset socket.| ...defines only the socket type. | ...should have the same name as the dedicated entity for default-configuration.</question>
<question title="Component instantiation..." type="checkbox"> ...generates the socket of the component type.| ...wires the socket (=component) to the PCB (=entity).</question>
<question title="Concurrent statement..." type="checkbox"> ...are declared only in the architecture.| ...are declared only in subprograms. | ...are executed consecutively.</question>
</quizlib>