====== IF Statement ======
===== Fundamentals =====

<code vhdl>
if CONDITION then
  -- sequential statements
end if;

if CONDITION then
  -- sequential statements
else
  -- sequential statements
end if;

if CONDITION then
  -- sequential statements
elsif CONDITION then
  -- sequential statements
...
else
  -- sequential statements
end if;
</code>

  * Condition is a boolean expression
  * Optional <text type="danger">else</text> path
    * Executed, if all conditions evaluate to false
  * Optional <text type="danger">elsif</text> sequence
    * Conditions may overlap
    * Priority

<note warning>Attention: **elsif** but **end if**</note>

<callout>
=== Notes ===
The if condition must evaluate to a boolean value (’true’ or ’false’). After the first if condition, any number of elsif conditions may follow. Overlaps may occur within different conditions. An else branch, which combines all cases that have not been covered before, can optionally be inserted last. The if statement is terminated with ’end if’.

The first if condition has top priority: if this condition is fulfilled, the corresponding statements will be carried out and the rest of the ’if - end if’ block will be skipped.
</callout>

===== IF Statement: Example =====
<code vhdl>
entity IF_STATEMENT is
   port (A, B, C, X : in bit_vector (3 downto 0);
         Z          : out bit_vector (3 downto 0));
end IF_STATEMENT;
</code>

<code vhdl>
architecture EXAMPLE1 of IF_STATEMENT is
begin

   process (A, B, C, X)
   begin 
    Z <= A;       -- default assignment for complete IF Statement
    if (X = "1111") then
      Z <= B;
    elsif (X > "1000") then
      Z <= C;

    end if;
  end process;

end EXAMPLE1;
</code>

<code vhdl>
architecture EXAMPLE2 of IF_STATEMENT is
begin

   process (A, B, C, X)
   begin 

    if (X = "1111") then
      Z <= B;
    elsif (X > "1000") then
      Z <= C;
    else
      Z <= A;     -- or else branch for complete IF Statement
    end if;
  end process;

end EXAMPLE2;
</code>

<callout>
=== Notes ===
The example code shows two different implementations of equivalent behavior.

The signal assignment to the signal Z in the first line of the left process (architecture EXAMPLE1) is called a default assignment, as its effects will only be visible if it is not overwritten by another assignment to Z.

Note that the two conditions of the ’if’ and ’elsif’ part overlap, because X="1111" is also true when X>"1000". As a result of the priority mechanism of this if construct, Z will receive the value of B if X="1111".
</callout>

===== IF Statement: Latch! =====
<code vhdl>
entity IF_STATEMENT is
   port (A, B, C, X : in bit_vector (3 downto 0);
         Z          : out bit_vector (3 downto 0));
end IF_STATEMENT;                  

architecture LATCH of IF_STATEMENT is
begin

   process (A, B, C, X)
   begin 
                    -- no clock present +
                    -- no default signal assignment for Z +
    if (X = "1111") then
      Z <= B;
    elsif (X > "1000") then
      Z <= C;
    end if;
                    -- not all values of X covered (no "else" branch) ➔ a LATCH gets inferred, yuck!
  end process;

end LATCH;
</code>

<note warning>When these three conditions come together: a LATCH gets inferred</note>

<panel type="info" title="VHDL RTL-Synthesis Standard (IEEE 1076.6:2004)" subtitle="">
**6.2.1.1 Level-sensitive storage from process with sensitivity list**

"A level-sensitive storage element (=Latch) shall be modeled for a signal (or variable) when all the following apply:
  - The signal (or variable) has an explicit assignment.
  - The signal (or variable) does not have an execution path with <clock_edge> as a condition.
  - There are executions that do not execute an explicit assignment to the signal (or variable)."
</panel>