====== Process Execution ======
===== Fundamentals =====
<code vhdl>
architecture A of E is
begin

  P1 : process
  begin
    -- sequential statements
  end process P1;

   -- C2: concurrent statements
 
 P2 : process
  begin
    -- sequential statements
  end process P2;

  -- C1: concurrent statements
end A;
</code>

{{:courses:system_design:vhdl_language_and_syntax:folie93_processexecution.svg?nolink&300|Process Execution}}

<callout>
=== Notes ===
An architecture can contain processes and concurrent statements which are all active in parallel. The connection of the parallel parts is established via signals and sensitivity lists. Concurrent statements can be interpreted as functionally equivalent processes with a sensitivity list containing all those values that are going to be read in this process. If, for example, the process P1 was triggered, e.g. by a clock edge, its statements are executed one after another. This way it is possible to execute parts of the code only after an active edge has occurred.

Let us assume that a couple of signals were modified. The changes will not take effect until the process execution has finished. According to the schematic, these updated values will trigger C1 and P1 which will trigger P1 and C2 in turn, and so on.

The execution of the statements continues until a stable state is reached, i.e. no events are generated any more.
</callout>

===== Concurrent versus Sequential Execution =====
<code vhdl>
architecture CONCURRENT of MULTIPLE is
  signal A, B, C, D : std_ulogic;
  signal Z : std_logic
begin
  Z <= A and B;
  Z <= C and D;
end CONCURRENT;
</code>
{{:courses:system_design:vhdl_language_and_syntax:folie94_concurrent.svg?nolink&200|Concurrent Execution}}

<code vhdl>
architecture SEQUENTIAL of MULTIPLE is
  signal Z, A, B, C, D : std_ulogic;
begin
  process (A, B, C, D)
  begin
    Z <= A and B;
    Z <= C and D;
  end process;
end SEQUENTIAL;
</code>
{{:courses:system_design:vhdl_language_and_syntax:folie94_sequential.svg?nolink&200|Sequential Execution}}

<callout>
=== Notes ===
If the same two signal assignments appear in the VHDL code, once as concurrent statement in the architecture and once in a process, the result will differ substantially:
  * In the first case, two parallel signal assignments are actually made to the signal. This is only allowed for resolved types, for which a so called resolution functions is present to decide which value is actually driven.
  * In the second case, the first assignment is executed and its result is stored. Afterwards, this result is overwritten by another assignment, so that only the last signal assignment is carried out.
</callout>

===== Signal Update =====
  * Signals have a **past** value, a **current** value and a **future** value
    * Future value used within the simulator core, only
    * Past value ≠ current value: event
  * Signal values are updated at the end of a process execution: the old current value of a signal is overwritten by the future value
  * Several process calls at one single moment of the simulation are possible

<callout>
=== Notes ===
The signal update mechanism is essential for a VHDL simulator. Signals possess a past, a current and a future value within the simulators signal management functions. Signal assignments in a process always assign the value to the future value of the signal.

The future value is copied to the current value in the signal update phase after the process execution is finished i.e. the process is suspended.

Several process calls at one signal moment of the simulation are possible?

Several process calls at one single moment of the simulation are possible!
</callout>

===== Delta Cycles (1) =====
{{:courses:system_design:vhdl_language_and_syntax:folie96_deltacycles.svg?nolink&500|Delty Cycles}}

  * One moment of simulation
  * One loop cycle = “delta cycle”
  * Delta time is orthogonal to simulation time
  * Signals are updated
  * All processes are initiated
    * Signal assignments are stored
  * New signal assignments
    * To execute further processes

<callout>
=== Notes ===
A simulation cycle always consists of a signal update and a process execution phase. Several of these so called delta cycles may have to be carried out in order to achieve a stable state of the system. The number of delta cycles has no effect on the time in the simulated time frame! It just affects the time that is necessary to carry out the simulation. The delta cycles are lined up orthogonally to the simulation time.
</callout>

===== Delta Cycles (2) =====
  * Several delta cycles at any moment of the simulation

{{:courses:system_design:vhdl_language_and_syntax:folie97_deltacycles.svg?nolink&700|Delta Cycles}}

<callout>
=== Notes ===
At the beginning, all signals are updated and a list of all processes that are triggered by the signal changes is created. All the processes of this list are executed one after another in delta cycle 1. When the execution is finished, the signal updates will be carried out and a new process list will be created. This continues until the process list remains empty, that means no further processes are triggered by the signal events. Now, statements which induce a real time step (’wait for ...’, ’... after ...’) are carried out and the simulation time advances for the specified amount of time.
</callout>

===== Delta Cycles - Example =====
<code vhdl>
library IEEE;                     
use IEEE.Std_Logic_1164.all;   
 
 entity DELTA is                      
 port (A, B : in std_ulogic;      
       Y, Z : out std_ulogic);     
end DELTA;
</code>
<code vhdl>
architecture EXAMPLE of DELTA is 
 signal X : std_ulogic;
begin
 process (A, B, X) 
 begin
  Y <= A;
  X <= B;
  Z <= X;
 end process;
end EXAMPLE;
</code>

  * Event on B (first delta cycle), future value of 
    * Y receives the current value of A (no change)
    * X receives the current value of B ( new value)
    * Z receives the current value of X (no change)
  * signal update
  * Event on X (second delta cycle), future value of
    * Y receives the current value of A (no change)
    * X receives the current value of B (no change)
    * Z receives the current value of X (new value)
  * signal update
  * No future events on A, B, X

<callout>
=== Notes ===
Let us assume that the value of signal B changes. In the example, the process is triggered by this event on B and is activated for the first time. The future value of X is given the current value of B. At the end of the process, the future value of X is transferred to its current value.

This change of value on X results in an event that calls the process for the second time. Now, the current value of X is written to the future value of Z (B and X remain the same). During the signal update phase only Z’s value changes which is not listed in the sensitivity list, i.e. the process will not be called again. The signals X and Z are set to the value from B this way. This example is for demonstrative purposes, only. The intermediate signal X conceals the functionality of the process and would not be used in practice. Generally, variables, which are not subject to the update mechanism, should be used instead.
</callout>

===== Process Behavior =====
| <code vhdl>
process (A, B) 
begin          
  if (A=B) then  
    Z <= ‘1’;       
  else           
    Z <= ‘0’;       
  end if;
  
end process;
</code> | <code vhdl>
process 
begin          
  if (A=B) then  
    Z <= ‘1’;       
  else           
    Z <= ‘0’;       
  end if;  
wait on A, B;       
end process; 
</code> |

  * The process is an endless loop
  * It is stopped by a wait-statement
  * The sensitivity list is equivalent to a wait-statement
  * A process with a sensitivity list must not contain any wait statement

<callout>
=== Notes ===
Basically, a process has to be considered as an endless loop.

The continuous process execution can be interrupted via wait statements. The use of a sensitivity list is equivalent to a WAIT ON-statement. If a sensitivity list is present, WAIT statements must not appear in the process.
</callout>

===== Postponed Process =====
<code vhdl>
postponed process
begin
  Z <= ‘0’ ;    -- wrong
  wait for 0 ns;
  Z <= ‘1’ ;    -- wrong
  wait on A, B; -- wrong
end process;
</code>

<code vhdl>
postponed process (A, B)
begin
  if (A=B) then
    Z <= ‘1’ after 5 ns;
  else
    Z <= ‘0’ after 4 ns;
  end if;
end process;
</code>

  * Processes which are executed in the last delta cycle of a certain moment
  * The following is not permitted:
    * Wait statements of the time 0
    * Signal assignments without delay (for 0 ns)

{{:courses:system_design:vhdl_language_and_syntax:folie107_postponedprocess.svg?nolink&400|Postponed Process}}

<note warning>Postponed processes are a new feature of VHDL’93</note>

<callout>
=== Notes ===
Postponed processes are always carried out in the last delta cycle.

This means that this process can access already stable signals at this point of simulation time.

In postponed processes, WAIT statements with 0 ns and signal assignments without delay are not permitted.

Please note that postponed processes can only be used in simulation, not in synthesis.
</callout>

===== Quiz =====
<quizlib id="quizprocessexecution" rightanswers="[['a2'],['a0','a1']]" submit="Check answers">
<question title="A delta cycle..." type="checkbox"> ...is the minimum timestep in a simulation.| ...updates exactly one signal.| neither of them</question>
<question title="A process..." type="checkbox"> ...is executed concurrently together with other processes and concurrent statements| ...can be controlled by wait statement or sensitivity list</question>
</quizlib>