====== Quiz ======
<code vhdl>
signal A_BUS, B_BUS, Z_BUS :        bit_vector (3 downto 0);
signal A_BIT, B_BIT, C_BIT, D_BIT : bit;
signal BYTE :                       bit_vector (7 downto 0);
</code>

<quizlib id="quizextendeddatatypes" rightanswers="[['a0'],['a1'],['a0','a1','a3'],['a1','a2'],['a0','a2']]" submit="Check answers">
<question title="Array assignment are made..." type="radio"> ...according to the position per default.| ...according to the index per default.| ...at option.</question>
<question title="A BIT_VECTOR assignment is e.g., ..." type="checkbox"> ...&lt;= "00111XXUUU00";| ...&lt;= "0000111000111"</question>
<question title="Which assignment are correct with the above definitions?" type="checkbox"> BYTE &lt;= (others = &gt; '1');| BYTE(7 downto 4) &lt;= A_BIT &amp; B_BIT &amp; A_BIT &amp; B_BIT;| Z_BUS &lt;= A_BIT &amp; B_BIT; | BYTE(3 downto 0) &lt;= ('1', B_BIT, '0', D_BIT); | A_BUS(0 to 1) &lt;= (others =&gt; '0'); </question>
<question title="Multivalued datatypes ..." type="checkbox"> ... have always a resolution function| ... are enumeration types | ... can be concatenated to arrays or records</question>
<question title="Several signals of a data type ..." type="checkbox"> ... that is not resolved must not drive a signal output signal of that type| ... can build an array, but not a record | ... can be assigned to (parts of) a bus of the appropriate vector type. </question>
</quizlib>