====== Timing behavior ======
===== Fundamentals =====
important for the ASIC Synthesis:
  * Input-Setup-Time TSU
  * Input-Hold-Time TH
  * Output-Delay-Time TOD
  * Wire-Delay-Time (spez. Clock Skew)

===== Setup/Hold-Time =====
{{:courses:system_design:synthesis:master-slave_flip-flop:folie350_dffcircuitvoltages.svg?nolink&600|Voltages}}

{{:courses:system_design:synthesis:master-slave_flip-flop:folie350_voltagepoints.svg?nolink&400|Voltage Points}}

{{:courses:system_design:synthesis:master-slave_flip-flop:folie350_setupholdtime.svg?nolink&250|Setup/Hold-Time}}

D stable while 
  * T<sub>SU</sub> before the clock edge and 
  * T<sub>H</sub> after the clock edge
that is all nodes in master part become stable values/levels

===== Output-Delay-Time =====
{{:courses:system_design:synthesis:master-slave_flip-flop:folie351_blockcircuit.svg?nolink&700|Block Circuit}}

{{:courses:system_design:synthesis:master-slave_flip-flop:folie351_outputdelaytime.svg?nolink&400|Output-Delay-Time}}

**Output-Delay-Time:** T<sub>OD</sub> delay at gate output

**Problem:** gates are faster (in relation to wires)

T<sub>OD</sub> ↓ but T<sub>skew</sub> ↑

**Static-Timing-Analysis:** checking after layout if the sum of all output-delays and real wire-delay-times results in  setup/hold-time violations

===== Synchronous design with VHDL =====
<code vhdl>
port (
    RESET   : in std_ulogic;
   CLK      : in std_ulogic;
   Q        : buffer std_logic_vector (3 downto 0)
);
</code>

<code vhdl>
process (CLK)
begin
   if CLK'event and CLK='1' then    -- rising clock
    if RESET = '1' then
      Q <= "0000";                  -- synchronous Reset (Setup/Hold Time!!)
    else
      Q <= Q + "0001";              -- count ("sequential state", Next-State-Logic)
    end if;
   end if;
end process;
</code>