====== RS flip-flop ======
===== Introduction =====
{{:courses:system_design:synthesis:master-slave_flip-flop:folie320_rsffcircuit.svg?nolink&500|RS-Flipflop Circuit}}

^ S ^ R ^ C  ^ Q(t+1) ^ state     ^
| 0 | 0 | ⎍ | Q(t)   | hold      |
| 0 | 1 | ⎍ | 0      | reset     |
| 1 | 0 | ⎍ | 1      | set       |
| 1 | 1 | ⎍ | <text type="danger">-</text> | <text type="danger">undefined</text> |

⎍ = while clock is HIGH

  * 2 statically clocked  RS-Latches (clocked, state-driven)
  * complementary controlled by clock C
  - C=1:
    * Master free : R/S is loaded  in master (while clock = 1)
    * Slave blocked : stores previous  master value
  - C=0:
    * Master blocked : <text type="primary">stores last R/S-state of HIGH-phase</text>
    * Slave free : <text type="primary">enables value of master (1.) to the output</text>

  - ⎍ positive periode of clock cycle: store  data
  - ↓ falling edge of clock: transmit data

===== RS Flip-Flop - timing behavior =====
  - positive period: hold data
  - negative edge: transfer data 

{{:courses:system_design:synthesis:master-slave_flip-flop:folie321_timingbehavior.svg?nolink&700|RS Flipflop Timing Behavior}}

{{:courses:system_design:synthesis:master-slave_flip-flop:folie324_rshighclockhigh.svg?nolink&550|RS high, Clock high, Slave holds}}

assumption: ideal gate switching time

<callout>
=== Notes ===
assuming R=S=1

C=1

Slave holds the old values of Q and Qn (which we don't know, and which are not equal)
</callout>

{{:courses:system_design:synthesis:master-slave_flip-flop:folie326_rshighclocklowafterfirstgatelevel.svg?nolink&550|RS high, Clock low, Slave transfers, first level of gates updates its values}}

<callout>
=== Notes ===
Clock toggles

Slave is "open" and transfers data to the outputs

first internal Master NAND output gets "1"

first internal Slave NAND output gets "0"
</callout>

{{:courses:system_design:synthesis:master-slave_flip-flop:folie328_rshighclocklowaftersecondgatelevel.svg?nolink&550|RS high, Clock low, Slave transfers, second level of gates updates its values}}

<callout>
=== Notes ===
Master: Q==Qn=1

Slave: Q==Qn=1

UNDEFINED!!!

Let's look at the internal Q/Qn

The "0"  is transferred to the input of the NANDs
(this happens simultaneously to the previous discussed transfer of data to the outputs)
</callout>

{{:courses:system_design:synthesis:master-slave_flip-flop:folie329_rshighclocklowafterslavegates.svg?nolink&550|RS high, Clock low, Slave transfers, slave gates update their values}}

**<text type="danger">t<sub>d</sub> later: Q nodes/outputs change values</text>**

<callout>
=== Notes ===
Again: data is transfered to the outputs
  * Master: Q==Qn=0
  * Slave: Q==Qn=0
  * UNDEFINED!!!

t<sub>d</sub> later: and again etc.
  * Master: Q==Qn=1
  * Slave: Q==Qn=1
  * UNDEFINED!!!
</callout>

===== RS Flip-Flop - timing behavior at R=S=1 =====

{{:courses:system_design:synthesis:master-slave_flip-flop:folie331_rshighclocklowfeedbackdelay.svg?nolink&550|oszillates generally with delay of feedbacks}}

**<text type="danger" size="large">t<sub>d</sub> runtime/delay of feedbacks</text>**

**<text type="danger" size="large">oszillates generally with t<sub>d</sub></text>**
<text type="danger" size="medium">(behavior depends on the other timing parameters too)</text>

===== RS Flip-Flop - summary =====
  * R=S=1 is undefined and is to avoid
  * Design of Cross-coupled NAND is difficult, Racing-Conditions - runtimes!
  * is not used in CMOS ASIC Design

===== RS Flip-Flop - Edge Triggered =====
{{:courses:system_design:synthesis:master-slave_flip-flop:folie338_rsffcircuit.svg?nolink&500|RS-FF Circuit}}

Q(t+1)=[R’ and (S or (S’ and Q))](t)

^ S ^ R ^ C ^ Q(t+1) ^ state     ^
| 0 | 0 | ↑ | Q(t)   | hold      |
| 0 | 1 | ↑ | 0      | reset     |
| 1 | 0 | ↑ | 1      | set       |
| 1 | 1 | ↑ | <text type="danger">-</text> | <text type="danger">avoid</text> |

↑ = rising edge of clock

{{:courses:system_design:synthesis:master-slave_flip-flop:folie338_timingbehavior.svg?nolink&700|triggering function is "good natured": R=S=1 results D=0 (Reset has priority)}}

<callout>
=== Notes ===
instead of "avoiding" R=S=1 we do a "reset" - it's nicer :-)
</callout>