====== D-FF ======
===== Overview =====
{{:courses:system_design:synthesis:master-slave_flip-flop:folie334_dffcircuit.svg?nolink&600|D-FF Circuit}}

^ D ^ C ^ Q(t+1) ^
| 1 | ↑ | 1      |
| 0 | ↑ | 0      |

↑ = rising edge of clock

  * **transmission-gates = simple switch:**
{{:courses:system_design:synthesis:master-slave_flip-flop:folie334_transmissiongate.svg?nolink&200|Transmission Gate}}

  * 2 complementary D-Latches are state controlled by clock
{{:courses:system_design:synthesis:master-slave_flip-flop:folie334_dffblock.svg?nolink&100|D-FF Block}}

  * C=0: <text type="primary">master is transparent, following the input level, slave is locked (holds)</text>
  * C=1: <text type="primary">Master is blocking, feeds immediately to the pos. edge of clock and the value seen on D is on the output immediately, Slave is transparent</text>

<text type="danger">Positive edge: Q = D      standard FF in CMOS-ASIC design!!</text>

{{:courses:system_design:synthesis:master-slave_flip-flop:folie335_dffsimulationflow.svg?nolink&700|D-FF Simulation Flow}}

===== D-FF in VHDL =====
<code vhdl>
D_FF: process (CLK)
begin
  if CLK'event and CLK='1' then
    Q <= D;
  end if;
end process;
</code>

<code vhdl>
D_LATCH: process (CLK, D)
begin
  if CLK='1' then
    Q <= D;
  end if;
end process;
</code>

<callout>
=== Notes ===
Here, a D-flip-flop controlled by a clock pulse edge is described. If an event occurs at the clock signal and this event has the value ONE, the value of the pin D will be transferred to the pin Q. (You could also await the negative clock pulse edge, then must be: CLK='0').
</callout>