====== FSM: Moore ======
===== Fundamentals =====
{{:courses:system_design:synthesis:finite_state_machines_and_vhdl:folie197_moorestatecircuit.svg?nolink&700|Moore State Circuit}}

  * The output vector is a function of the state vector: Y = f(S)

**Three Processes**
<code vhdl>
architecture RTL of MOORE is
   ...
begin
  REG: -- Clocked Process

  CMB: -- Combinational Process with Next State Logic

 OUTPUT: process (STATE)
    begin
        -- Output Logic
    end process OUTPUT;
end RTL ;
</code>

<note important>output logic</note>

<callout>
=== Notes ===
Here, an example of a Moore machine is shown.

The value of the output vector is a function of the current state.

This is the reason for the second logic block in the block diagram, located after the storing elements. This logic block holds the hardware which is needed to calculate the output values out of the current state of the automaton.

In the VHDL source code, this logic is implemented with an own combinational process.

As the value of the output vector depends on the current value of the state vector, only, no other signals appear in the sensitivity list of the process.
</callout>

===== Moore Example =====
{{:courses:system_design:synthesis:finite_state_machines_and_vhdl:folie198_moorestategraph.svg?nolink&500|Moore State Graph}}

<code vhdl>
architecture RTL of FSM_Moore is
  subtype STATE_TYPE is
    std_ulogic_vector(1 downto 0);
  constant START  : STATE_TYPE := "00";
  constant MIDDLE : STATE_TYPE := "11";
  constant STOP   : STATE_TYPE := "10";
  signal   STATE, NEXTSTATE : STATE_TYPE;
begin
  REG : process (CLK, RESET) begin
    if RESET = '1' then
      STATE <= START;
    elsif (CLK'event and CLK = '1') then
      STATE <= NEXTSTATE;
    end if;
  end process REG;

  CMB : process (A, B, STATE) begin
     NEXTSTATE <= STATE;
    case STATE IS
      when START =>
        if (A nor B) = '1' then
          NEXTSTATE <= MIDDLE;
        end if;
      when MIDDLE =>
        if (A and B) = '1' then
          NEXTSTATE <= STOP;
        end if;
      when STOP =>
        if (A xor B) = '1' then
          NEXTSTATE <= START;
        end if;
      when others =>
        NEXTSTATE <= START;
    end case;
  end process CMB;
  -- concurrent signal assignments 
  -- for output
  Y <= '1' when STATE = MIDDLE
       else '0';
  Z <= '1' when STATE = MIDDLE or
       STATE = STOP else '0';
end architecture RTL;
</code>

<callout>
=== Notes ===
Again, the bubble diagram and the corresponding VHDL code are shown; this time for a Moore automaton.

The difference to the Medvedev automaton can be recognized in the difference between the state encoding and the corresponding values for the output vector.

Both values are specified in the bubbles. The values for the output vector (Y, Z) are the same as in the Medvedev automaton. The state encoding is again based upon a binary code.

In the VHDL source code, the output logic is implemented via separate concurrent signal assignments. One can see that the output values are calculated out of the state vector values.
</callout>

===== Waveform Moore Example =====
{{:courses:system_design:synthesis:finite_state_machines_and_vhdl:folie199_moorewaveform.png?nolink&600|Moore Waveform}}

  * (Y,Z) changes simultaneously with STATE ⇒ Moore machine

<callout>
=== Notes ===
Again, the characteristics of the Moore automaton can be seen clearly in the waveform.

The values of the output vector change simultaneously with the values of the state vector. But this time the values of the output vector differ from those of the state vector.
</callout>