====== FSM and Simulation ======
===== Fundamentals =====
  * Simulation cycle consists of two phases
    * Signal update phase
    * Process execution phase

{{:courses:system_design:synthesis:finite_state_machines_and_vhdl:fsm_simulationcycle.svg?nolink&500|Simulytion Cycle}}

  * Combinational processes:
    * Signal update at any time
    * Process execution with new values and signal updates until no process execution necessary anymore
  * Clocked processes:
    * Signal update of CLOCK SIGNAL
    * Process execution with currently (old) values of inputs and following (combinational) process executions.
  * What if clock and inputs change at the same time?

===== Clocked Process Simulation (1) =====
  * FSM is fed with outputs from other registers

{{:courses:system_design:synthesis:finite_state_machines_and_vhdl:fsm_simulationfedbyregisters.svg?nolink&700|FSM is fed with outputs from other registers}}

  * X changes only after clock edge
  * STATE signal renewed before X changes ⇒ STATE takes over old value of NEXTSTATE
  * STATE = F( STATE<sub>old</sub>, X<sub>old</sub>)

===== Clocked Process Simulation (2) =====
  * FSM is fed with asynchronous inputs (X); TWO state processes

{{:courses:system_design:synthesis:finite_state_machines_and_vhdl:fsm_simulationfedasynchronous.svg?nolink&650|FSM is fed with asynchronous inputs}}

  * X can change together with clock edge
  * Physical world: STATE signal renewed before NEXTSTATE changes

^ RTL-Simulation: ^ Update<sub>n</sub> ^ Update<sub>n+1</sub> ^ STATE ^
|                 | CLK, ...           | X, ...               | F(STATE<sub>old</sub>, X<sub>old</sub>) |
|                 | CLK, X, ...        | ...                  | F(STATE<sub>old</sub>, X<sub>old</sub>) |
|                 | X, ...             | CLK, ...             | F(STATE<sub>old</sub>, X<sub>new</sub>) |

===== Clocked Process Simulation (3) =====
  * FSM is fed with asynchronous inputs (X); ONE state process

{{:courses:system_design:synthesis:finite_state_machines_and_vhdl:fsm_simulation1state.svg?nolink&650|FSM is fed with asynchronous inputs}}

  * X can change together with clock edge
  * Physical world: STATE signal renewed before NEXTSTATE changes

^ RTL-Simulation: ^ Update<sub>n</sub> ^ Update<sub>n+1</sub> ^ STATE ^
|                 | CLK, ...           | X, ...               | F(STATE<sub>old</sub>, X<sub>old</sub>) |
|                 | CLK, X, ...        | ...                  | F(STATE<sub>old</sub>, X<sub>new</sub>) |
|                 | X, ...             | CLK, ...             | F(STATE<sub>old</sub>, X<sub>new</sub>) |

===== Recommodations for Simulation =====
  * Don't assign stimulis together with clock edge
  * Use two state processes
  * Use concurrent signal assignments for clock generation (⇒ will be updated in prior Δ-Cycles than processes)

| <code vhdl>
CLK <= not CLK after PERIOD/2 ;
</code> | <code vhdl>
process begin
    CLK <= not CLK ;
    wait for PERIOD/2 ;
end process ;
</code> |
| Δ<sub>m,n</sub> ⇒ CLK in update list for Δ<sub>m+i,1</sub> \\ Δ<sub>m+i,1</sub> ⇒ CLK update | Δ<sub>m,n</sub> ⇒ CLK update (because of wait ...) \\ Δ<sub>m+i,1</sub> ⇒ Update of signals in update list ⇒ Process execution \\ Δ<sub>m+i,2</sub> => CLK update |