====== Combinational Logic ======
===== Feedback Loops =====
<code vhdl>
architecture EXAMPLE of FEEDBACK is
  
  signal B, X : integer range 0 to 99;
 
begin

  process (X, B)
  begin
   X <= X + B;
  end process;

...

end EXAMPLE;
</code>

{{:courses:system_design:synthesis:combinational_logic:folie271_feedbackloops.svg?nolink&300|Feedback Loops}}

<note warning>Do not create combinational feedback loops!</note>

<callout>
=== Notes ===
When modelling purely combinational logic, it is necessary to avoid combinational feedback loops. A feedback loop triggers itself all the time, i.e. the corresponding process is always active. In the example, this results in a perpetual addition, i.e. X is increased to its maximum value. So simulation quits at time 0 ns with an error message because X exceeds its range. In general, synthesis is possible, yet the hardware is not useable. 
</callout>

===== Coding Style Influence =====
|                         ^ Code ^ Hardware realization ^
^ Direct implementation   | <code vhdl>
EXAMPLE1:
process (SEL, A, B, C)
begin
   if SEL = ‘1’ then
     Z <= A + B;
   else
     Z <= A + C;
   end if;
end process EXAMPLE1;
</code> | {{:courses:system_design:synthesis:combinational_logic:folie272_directimplementation.svg?nolink&250|Direct Implementation}} |
^ Manual resource sharing | <code vhdl>
EXAMPLE2:
process (SEL, A, B, C)
  variable TMP : bit;
begin
   if SEL = ‘1’ then
     TMP := B;
   else
     TMP := C;
   end if;
Z <= A+ TMP;
end process EXAMPLE2;
</code> | {{:courses:system_design:synthesis:combinational_logic:folie272_manualresourcesharing.svg?nolink&250|Manual Resource Sharing}} |

<callout>
=== Notes ===
An IF statement is synthesized to a multiplexer with eventual additional logic. That is the reason why the direct implementation of example 1 results in two adders as this is exactly what the VHDL code describes. But it is obvious that one adder is sufficient to implement the desired functionality and good synthesis tools will detect this during their optimization cycles.

In example 2 a temporal variable is used to implement a functionally equivalent description which requires only one adder. Manual resource sharing is recommended as it leads to a better starting point for the synthesis process.

The structure of the generated hardware, at least in the first synthesis iteration, is determined by the VHDL code itself. Consequently, the coding style has a rather big impact on the optimization algorithms. As not all synthesis tools are able to optimize the design structure itself, it is reasonable to ease their task, e.g. by structuring the code for minimum critical paths.
</callout>

===== Source Code Optimization =====
  * An operation can be described very efficiently for synthesis, e.g.:

| <code vhdl>OUT1 <= IN1+IN2+IN3+IN4+IN5+IN6</code> | <code vhdl>OUT2 <= ((IN1+IN2)+(IN3+IN4))+(IN5+IN6)</code> |
| {{:courses:system_design:synthesis:combinational_logic:folie273_longpath.svg?nolink&220|Long Path}} | {{:courses:system_design:synthesis:combinational_logic:folie273_shortpath.svg?nolink&275|Short Path}} |

  * In one description the longest path goes via five, in the other description via three addition components - some optimization tools automatically change the description according to the given constraints.