====== Differences in Synthesis ======
===== Synthesis of Operators =====
  * Operator structure
    * Discrete gates
    * Macro cell from the library
  * Operator architecture (e.g. ripple-carry, carry-look-ahead etc.)
    * Specific comments for the synthesis tool contained in the VHDL code
    * Optimization based on time-/area-constraints

<callout>
=== Notes ===
Based on the operator symbol, the synthesis knows about the desired functionality.

Depending on the target technology and the corresponding library elements either a sort of submodule which performs the necessary operations is created out of standard cells, or a macro cell that has already been optimized by the manufacturer is instantiated in the netlist.

If alternative implementations exist, e.g. ripple-carry or carry-look-ahead, the decision will be made according to the given speed and area constraints. Sometimes, the user may influence the synthesis process via tool options or special VHDL comments that are evaluated by the software.
</callout>

===== IF Structure <-> CASE Structure =====
  * Different descriptions are synthesized differently

| <code vhdl>
...
if(INPUT > 17) then
  OUT1 <= A;
elsif (INPUT < 17);
  OUT1 <= B;
else
  OUT1 <= C;
end if ;
...
</code> | <code vhdl>
...
case INPUT is
when 0 to 16 =>
  OUT2 <= B;
when 17 =>;
  OUT2 <= C;
when others =>
  OUT2 <= A;
end case ;
...
</code> |
| {{:courses:system_design:synthesis:combinational_logic:folie281_ifstructure.svg?nolink&300|IF Structure}} | {{:courses:system_design:synthesis:combinational_logic:folie281_casestructure.svg?nolink&325|Case Structure}} |

<callout>
=== Notes ===
While algorithms can take care of some huge VHDL constructs, other model aspects can not be changed during synthesis. 

The use of IF constructs, for example, implies different levels of priority, i.e. they infer a hierarchical structure of multiplexers. 

In CASE statements, however, the different choice options do not overlap and a parallel structure with a single switching stage is the result.
</callout>

===== Implementation of a Data Bus =====
<code vhdl>
entiy TRISTATE is
   port (DATA1, DATA2: in std_ulogic;
         EN1, EN2    : in std_ulogic;
         DATA_BUS    :out std_logic;
end TRISTATE;
</code>

{{:courses:system_design:synthesis:combinational_logic:folie282_implementationofadatabus.svg?nolink&350|Implementation of a Data Bus}}

| <code vhdl>
architecture RTL1 of TRISTATE is
begin
   process (DATA1, EN1)
   begin
     if EN1 = ‘1’ then
        DATA_BUS <= DATA1;
     else
        DATA_BUS <=’z’;
     end if;
   end process;
   process ( DATA2, EN2)
   begin
     if EN2 = ‘1’ then
        DATA_BUS <= DATA2;
     else
        DATA_BUS <= ‘z’;
     end if;
   end process;
end RTL;
</code> | <code vhdl>
architecture RTL2 of TRISTATE is
begin
 DATA_BUS <= DATA1 when EN1=’1’ else ’z’;
 Data_BUS <= DATA2 when EN2=’1’ else ’z’;
end RTL2;
</code> |

<callout>
=== Notes ===
In order to implement a proper internal bus system it must be guaranteed that only one driver is active while all others are set to high impedance, i.e. driving ’Z’.

Otherwise, if one bus member drives a logic ’1’ and another drives a logic ’0’, the current might, depending on the actual technology, increase beyond acceptable levels and probably result in a permanent damage of the device.
</callout>

===== Problems with internal Bus Structures =====
**Bus with tristate drivers**

{{:courses:system_design:synthesis:combinational_logic:folie283_busblockdiagram.svg?nolink&300|Block Diagram}}

**Waveform**

{{:courses:system_design:synthesis:combinational_logic:folie283_waveform.svg?nolink&300|Waveform}}

  * Different propagation delays
  * A bus controller has to guarantee that at most one driver is active on the bus
  * Technology dependency

<callout>
=== Notes ===
This overlap of active drivers may be caused by different propagation delays, that means the deactivation of one driver takes more time than the activation of another one.

As a consequence two drivers are active. Even if the delays are balanced so that everything works properly, a change to another technology will likely induce problems with the delays.
</callout>

===== Portable and Safe Bus Structure =====
  * Multiplexer instead of tristate driver to avoid unbalanced tristate enables
  * Three internal signal (DIN, DOUT, DOUT_EN)
  * Bidirectional I/O pad
  * Benefit
    * Safe circuit
    * Portable and testable

{{:courses:system_design:synthesis:combinational_logic:folie284_safebusstructure.svg?nolink&750|Portable and Safe Bus Structure}}

<callout>
=== Notes ===
An alternative design structure avoids the problems associated with tristate signals:
  * Multiplexers, driven by the enable signals, guarantee that only one driver exists per signal. Bidirectional signals are eliminated internally by splitting the original bus into two parts. The bidirectional communication with the outside world is done by special I/O pads.
  * The core structure represents a safe circuit that is fully testable and easily ported to other technologies.
</callout>