====== Quiz ======
<quizlib id="quizsimulation" rightanswers="[['a0','a1'],['a2']]" submit="Check answers">
<question title="A testbench ..." type="checkbox"> ... does not need entity ports. | ... always contains component instantiations </question>
<question title="File I/O in VHDL" type="checkbox"> ... is possible without referencing additional packages | ... always significantly slows down the simulation | ... can be useful for analyzing simulation results </question>
</quizlib>